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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_trig_delay.vhd] - Diff between revs 274 and 275
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| Rev 274 |
Rev 275 |
| Line 33... |
Line 33... |
-- 0x1 AAAAAAAA Delay Time Byte 1 (RW)
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-- 0x1 AAAAAAAA Delay Time Byte 1 (RW)
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-- 0x2 AAAAAAAA Delay Time Byte 2 (RW)
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-- 0x2 AAAAAAAA Delay Time Byte 2 (RW)
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-- 0x3 AAAAAAAA Pulse Width Byte 0 (RW)
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-- 0x3 AAAAAAAA Pulse Width Byte 0 (RW)
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-- 0x4 AAAAAAAA Pulse Width Byte 1 (RW)
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-- 0x4 AAAAAAAA Pulse Width Byte 1 (RW)
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-- 0x5 AAAAAAAA Pulse Width Byte 2 (RW)
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-- 0x5 AAAAAAAA Pulse Width Byte 2 (RW)
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-- 0x6 EDCBAA-- Time Configuration (RW*)
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-- 0x6 EDCBAA-- Timer Configuration (RW*)
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-- A: Interrupt Select
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-- A: Interrupt Select
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-- 00 - Disabled
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-- 00 - Disabled
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-- 01 - Interrupt on trigger event
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-- 01 - Interrupt on trigger event
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-- 10 - Interrupt on delay done
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-- 10 - Interrupt on delay done
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-- 11 - Interrupt on pulse done
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-- 11 - Interrupt on pulse done
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