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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_trig_delay.vhd] - Diff between revs 275 and 292

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Line 21... Line 21...
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
-- VHDL Entity: o8_trig_delay
-- VHDL Entity: o8_trig_delay
-- Description: Programmable delay timer with time-base selection. Allows both
-- Description: Programmable delay timer with time-base selection. Allows both
--               they delay after triggering and pulse width to be set by
--               the delay after triggering and pulse width to be set by
--               software. Output may either be routed to a pin or used to
--               software. Output may either be routed to a pin or used to
--               trigger an interrupt.
--               trigger an interrupt.
--
--
-- Register Map:
-- Register Map:
-- Offset  Bitfield Description                        Read/Write
-- Offset  Bitfield Description                        Read/Write
Line 33... Line 33...
--   0x1   AAAAAAAA Delay Time  Byte 1                     (RW)
--   0x1   AAAAAAAA Delay Time  Byte 1                     (RW)
--   0x2   AAAAAAAA Delay Time  Byte 2                     (RW)
--   0x2   AAAAAAAA Delay Time  Byte 2                     (RW)
--   0x3   AAAAAAAA Pulse Width Byte 0                     (RW)
--   0x3   AAAAAAAA Pulse Width Byte 0                     (RW)
--   0x4   AAAAAAAA Pulse Width Byte 1                     (RW)
--   0x4   AAAAAAAA Pulse Width Byte 1                     (RW)
--   0x5   AAAAAAAA Pulse Width Byte 2                     (RW)
--   0x5   AAAAAAAA Pulse Width Byte 2                     (RW)
--   0x6   EDCBAA-- Timer Configuration                    (RW*)
--   0x6   FEDCBBA- Timer Configuration                    (RW*)
--                  A: Interrupt Select
--                  A: Global Interrupt Enable
--                   00 - Disabled
--                  B: Interrupt Select
--                   01 - Interrupt on trigger event
--                   00 - Interrupt on trigger input (pre-arm check)
 
--                   01 - Interrupt on trigger event (post-arm check)
--                   10 - Interrupt on delay done
--                   10 - Interrupt on delay done
--                   11 - Interrupt on pulse done
--                   11 - Interrupt on pulse done
--                  B: Trigger Edge
--                  C: Trigger Edge
--                    0 - Trigger on falling edge
--                    0 - Trigger on falling edge
--                    1 - Trigger on rising edge
--                    1 - Trigger on rising edge
--                  C: Automatic Re-Arm (enabled if 1)
--                  D: Automatic Re-Arm (enabled if 1)
--                  D: Time base locked (okay if 1)     (read-only)
--                  E: Time base locked (okay if 1)     (read-only)
--                  E: Time base source
--                  F: Time base source
--                    0 - Use the internal uSec_Tick pulse
--                    0 - Use the internal uSec_Tick pulse
--                    1 - Use an external clock source
--                    1 - Use an external clock source
--   0x7   DCBA---- Timer Control                          (RW*)
--   0x7   FEDCB--A Timer Control                          (RW*)
--                  A: Current output level             (read-only)
--                  A: External Trigger Input State     (read-only)
--                  B: Clear/Re-Arm on '1'              (one-shot)
--                  B: Issue Internal Trigger           (one-shot)
 
--                     Returns '0' on read
 
--                  C: Current output level             (read-only)
 
--                  D: Clear/Re-Arm on '1'              (one-shot)
--                     Trigger event status on read
--                     Trigger event status on read
--                  C: Disable/Safe Trigger             (one-shot)
--                  E: Disable/Safe Trigger             (one-shot)
--                     Returns '0' on read
--                     Returns '0' on read
--                  D: Enable/Arm Trigger               (one-shot)
--                  F: Enable/Arm Trigger               (one-shot)
--                     Trigger armed status on read
--                     Trigger armed status on read
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      05/14/20 Design start
-- Seth Henry      05/14/20 Design start
-- Seth Henry      05/18/20 Added write qualification input
-- Seth Henry      05/18/20 Added write qualification input
 
-- Seth Henry      05/27/21 Added internal trigger function
 
-- Seth Henry      05/27/21 Moved the arming logic to later in the trigger to
 
--                           allow premature trigger detection
 
-- Seth Henry      06/15/21 Added a global interrupt enable and modified the
 
--                           interrupt to use either the pre- or post-arm
 
--                           trigger input
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 79... Line 89...
  Default_Width              : std_logic_vector(23 downto 0) := x"000000";
  Default_Width              : std_logic_vector(23 downto 0) := x"000000";
  Default_Timebase           : std_logic := '0';
  Default_Timebase           : std_logic := '0';
  Default_Auto_ReArm         : std_logic := '0';
  Default_Auto_ReArm         : std_logic := '0';
  Default_Trigger_Edge       : std_logic := '1';
  Default_Trigger_Edge       : std_logic := '1';
  Default_Int_Source         : std_logic_vector(1 downto 0) := "00";
  Default_Int_Source         : std_logic_vector(1 downto 0) := "00";
 
  Default_Int_Enable         : std_logic := '0';
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Write_Qual                 : in  std_logic := '1';
  Write_Qual                 : in  std_logic := '1';
Line 132... Line 143...
  signal Time_Base_Source    : std_logic := '0';
  signal Time_Base_Source    : std_logic := '0';
  signal Time_Base_Status    : std_logic := '0';
  signal Time_Base_Status    : std_logic := '0';
  signal Auto_ReArm          : std_logic := '0';
  signal Auto_ReArm          : std_logic := '0';
  signal Trigger_Edge        : std_logic := '0';
  signal Trigger_Edge        : std_logic := '0';
  signal Interrupt_Select    : std_logic_vector(1 downto 0);
  signal Interrupt_Select    : std_logic_vector(1 downto 0);
 
  signal Interrupt_Enable    : std_logic := '0';
 
 
 
  signal Interrupt_Src       : std_logic := '0';
 
 
 
  signal Int_Trig            : std_logic := '0';
  signal Arm_Timer           : std_logic := '0';
  signal Arm_Timer           : std_logic := '0';
  signal Safe_Timer          : std_logic := '0';
  signal Safe_Timer          : std_logic := '0';
  signal Clear_Trigd         : std_logic := '0';
  signal Clear_Trigd         : std_logic := '0';
 
 
  -- Time Base signals
  -- Time Base signals
Line 147... Line 162...
 
 
  -- Trigger signals
  -- Trigger signals
  signal Ext_Trig_SR         : std_logic_vector(3 downto 0) := "0000";
  signal Ext_Trig_SR         : std_logic_vector(3 downto 0) := "0000";
  signal Trig_RE             : std_logic := '0';
  signal Trig_RE             : std_logic := '0';
  signal Trig_FE             : std_logic := '0';
  signal Trig_FE             : std_logic := '0';
  signal Delay_Trig          : std_logic := '0';
  signal Trigger_In          : std_logic := '0';
  signal Trigger_Armed       : std_logic := '0';
  signal Trigger_Armed       : std_logic := '0';
  signal Trigger_Event       : std_logic := '0';
  signal Trigger_Event       : std_logic := '0';
 
  signal Trigger_Event_q     : std_logic := '0';
 
  signal Delay_Trig          : std_logic := '0';
 
 
  -- Delay Timer signals
  -- Delay Timer signals
  signal Delay_Pending       : std_logic := '0';
  signal Delay_Pending       : std_logic := '0';
  signal Delay_Tmr           : std_logic_vector(23 downto 0) := x"000000";
  signal Delay_Tmr           : std_logic_vector(23 downto 0) := x"000000";
  signal Delay_Tmr_SR        : std_logic_vector(1 downto 0);
  signal Delay_Tmr_SR        : std_logic_vector(1 downto 0);
Line 185... Line 202...
      Pulse_Width            <= Default_Width;
      Pulse_Width            <= Default_Width;
      Time_Base_Source       <= Default_Timebase;
      Time_Base_Source       <= Default_Timebase;
      Auto_ReArm             <= Default_Auto_ReArm;
      Auto_ReArm             <= Default_Auto_ReArm;
      Trigger_Edge           <= Default_Trigger_Edge;
      Trigger_Edge           <= Default_Trigger_Edge;
      Interrupt_Select       <= Default_Int_Source;
      Interrupt_Select       <= Default_Int_Source;
 
      Interrupt_Enable       <= Default_Int_Enable;
 
      Int_Trig               <= '0';
      Arm_Timer              <= '0';
      Arm_Timer              <= '0';
      Safe_Timer             <= '0';
      Safe_Timer             <= '0';
      Clear_Trigd            <= '0';
      Clear_Trigd            <= '0';
      Interrupt              <= '0';
      Interrupt              <= '0';
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Reg_Sel_q              <= Reg_Sel_d;
      Reg_Sel_q              <= Reg_Sel_d;
 
 
      Wr_En_q                <= Wr_En_d;
      Wr_En_q                <= Wr_En_d;
      Wr_Data_q              <= Wr_Data_d;
      Wr_Data_q              <= Wr_Data_d;
 
 
 
      Int_Trig               <= '0';
      Arm_Timer              <= '0';
      Arm_Timer              <= '0';
      Safe_Timer             <= '0';
      Safe_Timer             <= '0';
      Clear_Trigd            <= '0';
      Clear_Trigd            <= '0';
 
 
      if( Wr_En_q = '1' and Write_Qual = '1' )then
      if( Wr_En_q = '1' and Write_Qual = '1' )then
Line 221... Line 241...
            Time_Base_Source <= Wr_Data_q(7);
            Time_Base_Source <= Wr_Data_q(7);
            -- Reserved for status bit
            -- Reserved for status bit
            Auto_ReArm       <= Wr_Data_q(5);
            Auto_ReArm       <= Wr_Data_q(5);
            Trigger_Edge     <= Wr_Data_q(4);
            Trigger_Edge     <= Wr_Data_q(4);
            Interrupt_Select <= Wr_Data_q(3 downto 2);
            Interrupt_Select <= Wr_Data_q(3 downto 2);
 
            Interrupt_Enable <= Wr_Data_q(1);
 
 
          when "111" =>
          when "111" =>
            Arm_Timer        <= Wr_Data_q(7);
            Arm_Timer        <= Wr_Data_q(7);
            Safe_Timer       <= Wr_Data_q(6);
            Safe_Timer       <= Wr_Data_q(6);
            Clear_Trigd      <= Wr_Data_q(5);
            Clear_Trigd      <= Wr_Data_q(5);
 
            Int_Trig         <= Wr_Data_q(3);
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
Line 260... Line 282...
          when "111" =>
          when "111" =>
            Rd_Data          <= Trigger_Armed &    -- Bit 7
            Rd_Data          <= Trigger_Armed &    -- Bit 7
                                '0' &              -- Bit 6
                                '0' &              -- Bit 6
                                Trigger_Event &    -- Bit 5
                                Trigger_Event &    -- Bit 5
                                Pulse_Out &        -- Bit 4
                                Pulse_Out &        -- Bit 4
                                "0000";            -- Bits 3:0
                                "000" &            -- Bits 3:1
 
                                Ext_Trig_SR(3);    -- Bit 0
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
      case( Interrupt_Select )is
      case( Interrupt_Select )is
        when "00" =>
        when "00" =>
          Interrupt          <= '0';
          Interrupt_Src      <= Trigger_In;
        when "01" =>
        when "01" =>
          Interrupt          <= Delay_Trig;
          Interrupt_Src      <= Delay_Trig;
        when "10" =>
        when "10" =>
          Interrupt          <= Width_Trig;
          Interrupt_Src      <= Width_Trig;
        when "11" =>
        when "11" =>
          Interrupt          <= Pulse_Done;
          Interrupt_Src      <= Pulse_Done;
        when others =>
        when others =>
          null;
          null;
      end case;
      end case;
 
 
 
      Interrupt              <= Interrupt_Src and Interrupt_Enable;
 
 
    end if;
    end if;
  end process;
  end process;
 
 
  Time_Base_proc: process( Clock, Reset )
  Time_Base_proc: process( Clock, Reset )
  begin
  begin
Line 308... Line 333...
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Ext_Trig_SR            <= (others => '0');
      Ext_Trig_SR            <= (others => '0');
      Trig_RE                <= '0';
      Trig_RE                <= '0';
      Trig_FE                <= '0';
      Trig_FE                <= '0';
      Delay_Trig             <= '0';
      Trigger_In             <= '0';
      Trigger_Armed          <= '0';
      Trigger_Armed          <= '0';
      Trigger_Event          <= '0';
      Trigger_Event          <= '0';
 
      Trigger_Event_q        <= '0';
 
      Delay_Trig             <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Ext_Trig_SR            <= Ext_Trig_SR(2 downto 0) & Ext_Trig;
      Ext_Trig_SR            <= Ext_Trig_SR(2 downto 0) & Ext_Trig;
 
 
      Trig_RE                <= Ext_Trig_SR(2) and not Ext_Trig_SR(3);
      Trig_RE                <= Ext_Trig_SR(2) and not Ext_Trig_SR(3);
      Trig_FE                <= Ext_Trig_SR(3) and not Ext_Trig_SR(2);
      Trig_FE                <= Ext_Trig_SR(3) and not Ext_Trig_SR(2);
 
 
      Delay_Trig             <= ((Trig_FE and not Trigger_Edge) or
      Trigger_In             <= ((Trig_FE and not Trigger_Edge) or
                                 (Trig_RE and Trigger_Edge)) and
                                 (Trig_RE and Trigger_Edge) or
                                Trigger_Armed and (not Trigger_Event);
                                  Int_Trig
 
                                );
 
 
      if( Arm_Timer = '1' )then
      if( Arm_Timer = '1' )then
        Trigger_Armed        <= '1';
        Trigger_Armed        <= '1';
      elsif( Safe_Timer = '1' )then
      elsif( Safe_Timer = '1' )then
        Trigger_Armed        <= '0';
        Trigger_Armed        <= '0';
      end if;
      end if;
 
 
      if( Delay_Trig = '1' )then
      if( Trigger_In = '1' )then
        Trigger_Event        <= '1';
        Trigger_Event        <= Trigger_Armed;
      elsif( Clear_Trigd = '1' or Auto_ReArm = '1' )then
      elsif( Clear_Trigd = '1' or Auto_ReArm = '1' )then
        Trigger_Event        <= '0';
        Trigger_Event        <= '0';
      end if;
      end if;
 
 
 
      -- Trigger on rising edge only
 
      Trigger_Event_q        <= Trigger_Event;
 
      Delay_Trig             <= Trigger_Event and (not Trigger_Event_q);
    end if;
    end if;
  end process;
  end process;
 
 
  Delay_proc: process( Clock, Reset )
  Delay_proc: process( Clock, Reset )
  begin
  begin

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