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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ts_ioctl.vhd] - Diff between revs 329 and 330

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Rev 329 Rev 330
Line 55... Line 55...
library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity o8_ts_ioctl is
entity o8_ts_ioctl is
generic(
generic(
  Default_Int_Mask           : ADDRESS_TYPE := x"0000";
 
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  --
  --
  PIT_Interrupt              : out std_logic;
  CPU_Interrupts             : out DATA_TYPE;
  --
  --
 
  RAM_Write_Fault            : in  std_logic;
  IO_Interrupts_In           : in  ADDRESS_TYPE := x"0000";
  IO_Interrupts_In           : in  ADDRESS_TYPE := x"0000";
  IO_Interrupt               : out std_logic;
  IO_Write_Qual_Out          : out ADDRESS_TYPE
  IO_Write_Qual              : out ADDRESS_TYPE
 
);
);
end entity;
end entity;
 
 
architecture behave of o8_ts_ioctl is
architecture behave of o8_ts_ioctl is
 
 
Line 86... Line 85...
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
 
 
  alias  Reg_Sel_d           is Open8_Bus.Address(2 downto 0);
  alias  Reg_Sel_d           is Open8_Bus.Address(2 downto 0);
  signal Reg_Sel_q           : std_logic_vector(2 downto 0);
  signal Reg_Sel_q           : std_logic_vector(2 downto 0);
  signal Wr_En_d             : std_logic;
  signal Wr_En_d             : std_logic := '0';
  signal Wr_En_q             : std_logic := '0';
  signal Wr_En_q             : std_logic := '0';
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Rd_En_d               : std_logic := '0';
  signal Rd_En_d               : std_logic := '0';
  signal Rd_En_q             : std_logic := '0';
  signal Rd_En_q             : std_logic := '0';
 
 
  signal Interval            : DATA_TYPE := x"00";
  signal Interval            : DATA_TYPE := x"00";
  signal Update_Interval     : std_logic;
  signal Update_Interval     : std_logic;
  signal Timer_Cnt           : DATA_TYPE := x"00";
  signal Timer_Cnt           : DATA_TYPE := x"00";
 
 
 
  signal PIT_Interrupt       : std_logic := '0';
 
 
  signal Int_Mask            : ADDRESS_TYPE := x"0000";
  signal Int_Mask            : ADDRESS_TYPE := x"0000";
  alias  Int_Mask_l          is Int_Mask(7 downto 0);
  alias  Int_Mask_l          is Int_Mask(7 downto 0);
  alias  Int_Mask_h          is Int_Mask(15 downto 8);
  alias  Int_Mask_h          is Int_Mask(15 downto 8);
 
 
  signal Clear_Pending       : ADDRESS_TYPE := x"0000";
  signal Clear_Pending       : ADDRESS_TYPE := x"0000";
  alias  Clear_Pending_l     is Clear_Pending(7 downto 0);
  alias  Clear_Pending_l     is Clear_Pending(7 downto 0);
  alias  Clear_Pending_h     is Clear_Pending(15 downto 8);
  alias  Clear_Pending_h     is Clear_Pending(15 downto 8);
 
 
  signal Ack_IO_Ints         : std_logic;
  signal Ack_IO_Ints         : std_logic := '0';
 
 
  signal Pending             : ADDRESS_TYPE := x"0000";
  signal Pending             : ADDRESS_TYPE := x"0000";
  alias  Pending_l           is Pending(7 downto 0);
  alias  Pending_l           is Pending(7 downto 0);
  alias  Pending_h           is Pending(15 downto 8);
  alias  Pending_h           is Pending(15 downto 8);
  signal Pending_q           : ADDRESS_TYPE := x"0000";
  signal Pending_q           : ADDRESS_TYPE := x"0000";
  signal Pending_RE          : ADDRESS_TYPE := x"0000";
  signal Pending_RE          : ADDRESS_TYPE := x"0000";
 
 
  signal IO_Int_Pending      : std_logic;
  signal IO_Int_Pending      : std_logic := '0';
 
 
 
  signal IO_Interrupt        : std_logic := '0';
 
 
  signal IO_Qual_Reg         : ADDRESS_TYPE := x"0000";
  signal IO_Qual_Reg         : ADDRESS_TYPE := x"0000";
  alias  IO_Qual_l           is IO_Qual_Reg(7 downto 0);
  alias  IO_Qual_l           is IO_Qual_Reg(7 downto 0);
  alias  IO_Qual_h           is IO_Qual_Reg(15 downto 8);
  alias  IO_Qual_h           is IO_Qual_Reg(15 downto 8);
 
 
begin
begin
 
 
  IO_Write_Qual              <= IO_Qual_Reg;
  -- The task switcher assumes the following CPU interrupt configuration
 
  CPU_Interrupts(0)          <= RAM_Write_Fault; -- WPR fault interrupt
 
  CPU_Interrupts(1)          <= PIT_Interrupt;   -- Pre-emption timer interrupt
 
  CPU_Interrupts(2)          <= IO_Interrupt;    -- Cascaded I/O interrupt
 
  CPU_Interrupts(7 downto 3) <= (others => '0'); -- Supervisor functions
 
 
 
  IO_Write_Qual_Out          <= IO_Qual_Reg;
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Wr_En_d                    <= Addr_Match and CPU_Wr_En and CPU_ISR_En;
  Wr_En_d                    <= Addr_Match and CPU_Wr_En and CPU_ISR_En;
  Rd_En_d                    <= Addr_Match and CPU_Rd_En;
  Rd_En_d                    <= Addr_Match and CPU_Rd_En;
 
 
Line 137... Line 146...
      Wr_Data_q              <= x"00";
      Wr_Data_q              <= x"00";
      Rd_En_q                <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Interval               <= x"00";
      Interval               <= x"00";
      Update_Interval        <= '0';
      Update_Interval        <= '0';
      Int_Mask               <= Default_Int_Mask;
      Int_Mask               <= x"0000";
      Clear_Pending          <= x"0000";
      Clear_Pending          <= x"0000";
      Ack_IO_Ints            <= '0';
      Ack_IO_Ints            <= '0';
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Reg_Sel_q              <= Reg_Sel_d;
      Reg_Sel_q              <= Reg_Sel_d;
      Wr_En_q                <= Wr_En_d;
      Wr_En_q                <= Wr_En_d;

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