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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_ts_ioctl is
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entity o8_ts_ioctl is
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generic(
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generic(
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Default_Int_Mask : ADDRESS_TYPE := x"0000";
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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PIT_Interrupt : out std_logic;
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CPU_Interrupts : out DATA_TYPE;
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--
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--
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RAM_Write_Fault : in std_logic;
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IO_Interrupts_In : in ADDRESS_TYPE := x"0000";
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IO_Interrupts_In : in ADDRESS_TYPE := x"0000";
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IO_Interrupt : out std_logic;
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IO_Write_Qual_Out : out ADDRESS_TYPE
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IO_Write_Qual : out ADDRESS_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_ts_ioctl is
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architecture behave of o8_ts_ioctl is
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
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signal Reg_Sel_q : std_logic_vector(2 downto 0);
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signal Wr_En_d : std_logic;
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Interval : DATA_TYPE := x"00";
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signal Interval : DATA_TYPE := x"00";
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signal Update_Interval : std_logic;
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signal Update_Interval : std_logic;
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signal Timer_Cnt : DATA_TYPE := x"00";
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signal Timer_Cnt : DATA_TYPE := x"00";
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signal PIT_Interrupt : std_logic := '0';
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signal Int_Mask : ADDRESS_TYPE := x"0000";
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signal Int_Mask : ADDRESS_TYPE := x"0000";
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alias Int_Mask_l is Int_Mask(7 downto 0);
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alias Int_Mask_l is Int_Mask(7 downto 0);
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alias Int_Mask_h is Int_Mask(15 downto 8);
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alias Int_Mask_h is Int_Mask(15 downto 8);
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signal Clear_Pending : ADDRESS_TYPE := x"0000";
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signal Clear_Pending : ADDRESS_TYPE := x"0000";
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alias Clear_Pending_l is Clear_Pending(7 downto 0);
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alias Clear_Pending_l is Clear_Pending(7 downto 0);
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alias Clear_Pending_h is Clear_Pending(15 downto 8);
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alias Clear_Pending_h is Clear_Pending(15 downto 8);
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signal Ack_IO_Ints : std_logic;
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signal Ack_IO_Ints : std_logic := '0';
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signal Pending : ADDRESS_TYPE := x"0000";
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signal Pending : ADDRESS_TYPE := x"0000";
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alias Pending_l is Pending(7 downto 0);
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alias Pending_l is Pending(7 downto 0);
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alias Pending_h is Pending(15 downto 8);
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alias Pending_h is Pending(15 downto 8);
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signal Pending_q : ADDRESS_TYPE := x"0000";
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signal Pending_q : ADDRESS_TYPE := x"0000";
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signal Pending_RE : ADDRESS_TYPE := x"0000";
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signal Pending_RE : ADDRESS_TYPE := x"0000";
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signal IO_Int_Pending : std_logic;
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signal IO_Int_Pending : std_logic := '0';
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signal IO_Interrupt : std_logic := '0';
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signal IO_Qual_Reg : ADDRESS_TYPE := x"0000";
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signal IO_Qual_Reg : ADDRESS_TYPE := x"0000";
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alias IO_Qual_l is IO_Qual_Reg(7 downto 0);
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alias IO_Qual_l is IO_Qual_Reg(7 downto 0);
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alias IO_Qual_h is IO_Qual_Reg(15 downto 8);
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alias IO_Qual_h is IO_Qual_Reg(15 downto 8);
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begin
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begin
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IO_Write_Qual <= IO_Qual_Reg;
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-- The task switcher assumes the following CPU interrupt configuration
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CPU_Interrupts(0) <= RAM_Write_Fault; -- WPR fault interrupt
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CPU_Interrupts(1) <= PIT_Interrupt; -- Pre-emption timer interrupt
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CPU_Interrupts(2) <= IO_Interrupt; -- Cascaded I/O interrupt
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CPU_Interrupts(7 downto 3) <= (others => '0'); -- Supervisor functions
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IO_Write_Qual_Out <= IO_Qual_Reg;
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and CPU_Wr_En and CPU_ISR_En;
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Wr_En_d <= Addr_Match and CPU_Wr_En and CPU_ISR_En;
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Rd_En_d <= Addr_Match and CPU_Rd_En;
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Rd_En_d <= Addr_Match and CPU_Rd_En;
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En_q <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Interval <= x"00";
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Interval <= x"00";
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Update_Interval <= '0';
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Update_Interval <= '0';
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Int_Mask <= Default_Int_Mask;
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Int_Mask <= x"0000";
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Clear_Pending <= x"0000";
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Clear_Pending <= x"0000";
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Ack_IO_Ints <= '0';
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Ack_IO_Ints <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_En_q <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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