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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm12.vhd] - Diff between revs 180 and 189
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| Rev 180 |
Rev 189 |
| Line 63... |
Line 63... |
);
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);
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end entity;
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end entity;
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architecture behave of o8_vdsm12 is
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architecture behave of o8_vdsm12 is
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
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retval := 1;
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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end loop;
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return retval;
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end function;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Reg_Addr is Bus_Address(1 downto 0);
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alias Reg_Addr is Bus_Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0);
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