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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm12.vhd] - Diff between revs 189 and 191
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| Rev 189 |
Rev 191 |
| Line 176... |
Line 176... |
io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel <= "00";
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Reg_Sel <= "00";
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= OPEN8_NULLBUS;
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_UB <= x"00";
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DAC_Val_UB <= x"00";
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DAC_Val <= (others => '0');
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DAC_Val <= (others => '0');
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| Line 201... |
Line 201... |
DAC_Val <= DAC_Val_UB(3 downto 0) & DAC_Val_LB;
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DAC_Val <= DAC_Val_UB(3 downto 0) & DAC_Val_LB;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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|
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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Rd_Data <= DAC_Val_LB;
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Rd_Data <= DAC_Val_LB;
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