| Line 25... |
Line 25... |
-- Description: 12-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
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-- Description: 12-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA Pending DAC Level (7:0) (R/W)
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-- 0x0 AAAAAAAA Pending DAC Level (7:0) (R/W)
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-- 0x1 AAAAAAAA Pending DAC Level (11:8) (R/W)
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-- 0x1 ----AAAA Pending DAC Level (11:8) (R/W)
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-- 0x2 -------- Clear DAC Output (on write) (WO)
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-- 0x2 -------- Clear DAC Output (on write) (WO)
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-- 0x3 AAAAAAAA Update DAC Output (on write) (RO)
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-- 0x3 AAAAAAAA Update DAC Output (on write) (RO)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/18/19 Design start
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-- Seth Henry 12/18/19 Design start
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-- Seth Henry 04/10/20 Code Cleanup
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 67... |
Line 68... |
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Reg_Addr is Bus_Address(1 downto 0);
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alias Reg_Addr is Bus_Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic;
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic;
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signal Rd_En : std_logic := '0';
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constant DAC_Width : integer := 12;
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constant DAC_Width : integer := 12;
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signal DAC_Val_LB : DATA_TYPE;
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signal DAC_Val_LB : std_logic_vector(7 downto 0) := x"00";
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signal DAC_Val_UB : DATA_TYPE;
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signal DAC_Val_UB : std_logic_vector(3 downto 0) := x"0";
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signal DAC_Val : std_logic_vector(DAC_Width-1 downto 0);
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signal DAC_Val : std_logic_vector(DAC_Width-1 downto 0) :=
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(others => '0');
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constant DELTA_1_I : integer := 1;
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constant DELTA_1_I : integer := 1;
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constant DELTA_2_I : integer := 5;
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constant DELTA_2_I : integer := 5;
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constant DELTA_3_I : integer := 25;
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constant DELTA_3_I : integer := 25;
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constant DELTA_4_I : integer := 75;
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constant DELTA_4_I : integer := 75;
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| Line 146... |
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constant PADJ_9 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_9 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_9_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_9_I,DIV_WIDTH);
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constant PADJ_10 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_10 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_10_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_10_I,DIV_WIDTH);
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signal DACin_q : std_logic_vector(DAC_Width-1 downto 0);
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signal DACin_q : std_logic_vector(DAC_Width-1 downto 0) :=
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(others => '0');
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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(others => '0');
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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signal diff : std_logic_vector(DIV_WIDTH downto 0);
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(others => '0');
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0) :=
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(others => '0');
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signal diff : std_logic_vector(DIV_WIDTH downto 0) :=
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(others => '0');
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constant CB : integer := ceil_log2(DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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signal count : std_logic_vector(CB-1 downto 0);
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signal count : std_logic_vector(CB-1 downto 0) :=
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(others => '0');
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signal Next_Width : std_logic_vector(DAC_Width-1 downto 0) :=
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(others => '0');
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signal Next_Period : std_logic_vector(DAC_Width-1 downto 0) :=
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(others => '0');
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signal Next_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Width : std_logic_vector(DAC_Width-1 downto 0) :=
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signal Next_Period : std_logic_vector(DAC_Width-1 downto 0);
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(others => '0');
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signal PWM_Width : std_logic_vector(DAC_Width-1 downto 0);
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signal PWM_Period : std_logic_vector(DAC_Width-1 downto 0) :=
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signal PWM_Period : std_logic_vector(DAC_Width-1 downto 0);
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(others => '0');
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signal Width_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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signal Width_Ctr : std_logic_vector(DAC_Width-1 downto 0) :=
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signal Period_Ctr : std_logic_vector(DAC_Width-1 downto 0);
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(others => '0');
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signal Period_Ctr : std_logic_vector(DAC_Width-1 downto 0) :=
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(others => '0');
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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| Line 180... |
Line 198... |
Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_UB <= x"00";
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DAC_Val_UB <= x"0";
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DAC_Val <= (others => '0');
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DAC_Val <= (others => '0');
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel <= Reg_Addr;
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Reg_Sel <= Reg_Addr;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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| Line 192... |
Line 210... |
if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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DAC_Val_LB <= Wr_Data_q;
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DAC_Val_LB <= Wr_Data_q;
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when "01" =>
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when "01" =>
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DAC_Val_UB <= "0000" & Wr_Data_q(3 downto 0);
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DAC_Val_UB <= Wr_Data_q(3 downto 0);
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when "10" =>
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when "10" =>
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DAC_Val <= (others => '0');
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DAC_Val <= (others => '0');
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when "11" =>
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when "11" =>
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DAC_Val <= DAC_Val_UB(3 downto 0) & DAC_Val_LB;
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DAC_Val <= DAC_Val_UB & DAC_Val_LB;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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| Line 208... |
Line 226... |
if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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Rd_Data <= DAC_Val_LB;
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Rd_Data <= DAC_Val_LB;
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when "01" =>
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when "01" =>
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Rd_Data <= DAC_Val_UB;
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Rd_Data <= x"0" & DAC_Val_UB;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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