| Line 52... |
Line 52... |
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
--
|
--
|
Bus_Address : in ADDRESS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Wr_Enable : in std_logic;
|
|
Wr_Data : in DATA_TYPE;
|
|
Rd_Enable : in std_logic;
|
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
--
|
--
|
PDM_Out : out std_logic
|
PDM_Out : out std_logic
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_vdsm12 is
|
architecture behave of o8_vdsm12 is
|
|
|
constant User_Addr : std_logic_vector(15 downto 2)
|
constant User_Addr : std_logic_vector(15 downto 2)
|
:= Address(15 downto 2);
|
:= Address(15 downto 2);
|
alias Comp_Addr is Bus_Address(15 downto 2);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
|
alias Reg_Addr is Bus_Address(1 downto 0);
|
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
|
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
|
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
|
signal Addr_Match : std_logic := '0';
|
signal Addr_Match : std_logic := '0';
|
signal Wr_En : std_logic := '0';
|
signal Wr_En : std_logic := '0';
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Rd_En : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
| Line 203... |
Line 200... |
DAC_Val_UB <= x"0";
|
DAC_Val_UB <= x"0";
|
DAC_Val <= (others => '0');
|
DAC_Val <= (others => '0');
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Reg_Sel <= Reg_Addr;
|
Reg_Sel <= Reg_Addr;
|
|
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Open8_Bus.Wr_Data;
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
case( Reg_Sel )is
|
case( Reg_Sel )is
|
when "00" =>
|
when "00" =>
|
DAC_Val_LB <= Wr_Data_q;
|
DAC_Val_LB <= Wr_Data_q;
|
when "01" =>
|
when "01" =>
|
| Line 220... |
Line 217... |
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
case( Reg_Sel )is
|
case( Reg_Sel )is
|
when "00" =>
|
when "00" =>
|
Rd_Data <= DAC_Val_LB;
|
Rd_Data <= DAC_Val_LB;
|
when "01" =>
|
when "01" =>
|
