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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm12.vhd] - Diff between revs 223 and 224

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Rev 223 Rev 224
Line 34... Line 34...
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      12/18/19 Design start
-- Seth Henry      12/18/19 Design start
-- Seth Henry      04/10/20 Code Cleanup
-- Seth Henry      04/10/20 Code Cleanup
 
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
Line 45... Line 46...
library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity o8_vdsm12 is
entity o8_vdsm12 is
generic(
generic(
  Reset_Level                : std_logic := '1';
  Default_Value              : std_logic_vector(11 downto 0) := x"000";
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Clock                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  --
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  --
  --
  PDM_Out                    : out std_logic
  DACOut                     : out std_logic
);
);
end entity;
end entity;
 
 
architecture behave of o8_vdsm12 is
architecture behave of o8_vdsm12 is
 
 
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Reset                is Open8_Bus.Reset;
 
 
  constant User_Addr         : std_logic_vector(15 downto 2)
  constant User_Addr         : std_logic_vector(15 downto 2)
                               := Address(15 downto 2);
                               := Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  alias  Reg_Addr            is Open8_Bus.Address(1 downto 0);
  alias  Reg_Addr            is Open8_Bus.Address(1 downto 0);
  signal Reg_Sel             : std_logic_vector(1 downto 0) := "00";
  signal Reg_Sel             : std_logic_vector(1 downto 0) := "00";
Line 196... Line 197...
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Wr_En                  <= '0';
      Wr_En                  <= '0';
      Wr_Data_q              <= x"00";
      Wr_Data_q              <= x"00";
      DAC_Val_LB             <= x"00";
      DAC_Val_LB             <= x"00";
      DAC_Val_UB             <= x"0";
      DAC_Val_UB             <= x"0";
      DAC_Val                <= (others => '0');
      DAC_Val                <= Default_Value;
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Reg_Sel                <= Reg_Addr;
      Reg_Sel                <= Reg_Addr;
 
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
Line 269... Line 270...
      DACin_q                <= (others => '0');
      DACin_q                <= (others => '0');
      PWM_Width              <= (others => '0');
      PWM_Width              <= (others => '0');
      PWM_Period             <= (others => '0');
      PWM_Period             <= (others => '0');
      Period_Ctr             <= (others => '0');
      Period_Ctr             <= (others => '0');
      Width_Ctr              <= (others => '0');
      Width_Ctr              <= (others => '0');
      PDM_Out                <= '0';
      DACOut                 <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      q                      <= diff(DIV_WIDTH-1 downto 0) &
      q                      <= diff(DIV_WIDTH-1 downto 0) &
                                q(DIV_WIDTH-2 downto 0) & '1';
                                q(DIV_WIDTH-2 downto 0) & '1';
      if( diff(DIV_WIDTH) = '1' )then
      if( diff(DIV_WIDTH) = '1' )then
        q                    <= q(DIV_WIDTH*2-2 downto 0) & '0';
        q                    <= q(DIV_WIDTH*2-2 downto 0) & '0';
Line 291... Line 292...
      end if;
      end if;
 
 
      Period_Ctr            <= Period_Ctr - 1;
      Period_Ctr            <= Period_Ctr - 1;
      Width_Ctr             <= Width_Ctr - 1;
      Width_Ctr             <= Width_Ctr - 1;
 
 
      PDM_Out               <= '1';
      DACOut                <= '1';
      if( Width_Ctr = 0 )then
      if( Width_Ctr = 0 )then
        PDM_Out             <= '0';
        DACOut              <= '0';
        Width_Ctr           <= (others => '0');
        Width_Ctr           <= (others => '0');
      end if;
      end if;
 
 
      if( Period_Ctr = 0 )then
      if( Period_Ctr = 0 )then
        Period_Ctr          <= PWM_Period;
        Period_Ctr          <= PWM_Period;

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