| Line 34... |
Line 34... |
-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/18/19 Design start
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-- Seth Henry 12/18/19 Design start
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-- Seth Henry 04/10/20 Code Cleanup
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-- Seth Henry 04/10/20 Code Cleanup
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 45... |
Line 46... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_vdsm12 is
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entity o8_vdsm12 is
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generic(
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generic(
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Reset_Level : std_logic := '1';
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Default_Value : std_logic_vector(11 downto 0) := x"000";
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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PDM_Out : out std_logic
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DACOut : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_vdsm12 is
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architecture behave of o8_vdsm12 is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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| Line 196... |
Line 197... |
Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_LB <= x"00";
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DAC_Val_UB <= x"0";
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DAC_Val_UB <= x"0";
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DAC_Val <= (others => '0');
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DAC_Val <= Default_Value;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel <= Reg_Addr;
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Reg_Sel <= Reg_Addr;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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| Line 269... |
Line 270... |
DACin_q <= (others => '0');
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DACin_q <= (others => '0');
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PWM_Width <= (others => '0');
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PWM_Width <= (others => '0');
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PWM_Period <= (others => '0');
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PWM_Period <= (others => '0');
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Period_Ctr <= (others => '0');
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Period_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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PDM_Out <= '0';
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DACOut <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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q <= diff(DIV_WIDTH-1 downto 0) &
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q <= diff(DIV_WIDTH-1 downto 0) &
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q(DIV_WIDTH-2 downto 0) & '1';
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q(DIV_WIDTH-2 downto 0) & '1';
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if( diff(DIV_WIDTH) = '1' )then
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if( diff(DIV_WIDTH) = '1' )then
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q <= q(DIV_WIDTH*2-2 downto 0) & '0';
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q <= q(DIV_WIDTH*2-2 downto 0) & '0';
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| Line 291... |
Line 292... |
end if;
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end if;
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Period_Ctr <= Period_Ctr - 1;
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Period_Ctr <= Period_Ctr - 1;
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Width_Ctr <= Width_Ctr - 1;
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Width_Ctr <= Width_Ctr - 1;
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PDM_Out <= '1';
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DACOut <= '1';
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if( Width_Ctr = 0 )then
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if( Width_Ctr = 0 )then
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PDM_Out <= '0';
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DACOut <= '0';
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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end if;
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end if;
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if( Period_Ctr = 0 )then
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if( Period_Ctr = 0 )then
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Period_Ctr <= PWM_Period;
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Period_Ctr <= PWM_Period;
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