| Line 35... |
Line 35... |
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 12/18/19 Design start
|
-- Seth Henry 12/18/19 Design start
|
-- Seth Henry 04/10/20 Code Cleanup
|
-- Seth Henry 04/10/20 Code Cleanup
|
-- Seth Henry 04/16/20 Modified to use Open8 bus record
|
-- Seth Henry 04/16/20 Modified to use Open8 bus record
|
|
-- Seth Henry 05/18/20 Added write qualification input
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 51... |
Line 52... |
Default_Value : std_logic_vector(11 downto 0) := x"000";
|
Default_Value : std_logic_vector(11 downto 0) := x"000";
|
Address : ADDRESS_TYPE
|
Address : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
|
Write_Qual : in std_logic := '1';
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
--
|
--
|
DACOut : out std_logic
|
DACOut : out std_logic
|
);
|
);
|
end entity;
|
end entity;
|
| Line 65... |
Line 67... |
alias Reset is Open8_Bus.Reset;
|
alias Reset is Open8_Bus.Reset;
|
|
|
constant User_Addr : std_logic_vector(15 downto 2)
|
constant User_Addr : std_logic_vector(15 downto 2)
|
:= Address(15 downto 2);
|
:= Address(15 downto 2);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
|
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
|
signal Addr_Match : std_logic;
|
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
|
|
signal Addr_Match : std_logic := '0';
|
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
|
signal Wr_En : std_logic := '0';
|
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
|
|
signal Wr_En_d : std_logic := '0';
|
|
signal Wr_En_q : std_logic := '0';
|
|
alias Wr_Data_d is Open8_Bus.Wr_Data;
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
signal Rd_En : std_logic := '0';
|
signal Rd_En_d : std_logic := '0';
|
|
signal Rd_En_q : std_logic := '0';
|
|
|
constant DAC_Width : integer := 12;
|
constant DAC_Width : integer := 12;
|
|
|
signal DAC_Val_LB : std_logic_vector(7 downto 0) := x"00";
|
signal DAC_Val_LB : std_logic_vector(7 downto 0) := x"00";
|
signal DAC_Val_UB : std_logic_vector(3 downto 0) := x"0";
|
signal DAC_Val_UB : std_logic_vector(3 downto 0) := x"0";
|
| Line 186... |
Line 192... |
(others => '0');
|
(others => '0');
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
|
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
|
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Sel <= "00";
|
Reg_Sel_q <= "00";
|
Rd_En <= '0';
|
Wr_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
|
Wr_En <= '0';
|
|
Wr_Data_q <= x"00";
|
Wr_Data_q <= x"00";
|
|
Rd_En_q <= '0';
|
|
Rd_Data <= OPEN8_NULLBUS;
|
|
|
DAC_Val_LB <= x"00";
|
DAC_Val_LB <= x"00";
|
DAC_Val_UB <= x"0";
|
DAC_Val_UB <= x"0";
|
DAC_Val <= Default_Value;
|
DAC_Val <= Default_Value;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Reg_Sel <= Reg_Addr;
|
Reg_Sel_q <= Reg_Sel_d;
|
|
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
Wr_En_q <= Wr_En_d;
|
Wr_Data_q <= Open8_Bus.Wr_Data;
|
Wr_Data_q <= Wr_Data_d;
|
if( Wr_En = '1' )then
|
if( Wr_En_q = '1' and Write_Qual = '1' )then
|
case( Reg_Sel )is
|
case( Reg_Sel_q )is
|
when "00" =>
|
when "00" =>
|
DAC_Val_LB <= Wr_Data_q;
|
DAC_Val_LB <= Wr_Data_q;
|
when "01" =>
|
when "01" =>
|
DAC_Val_UB <= Wr_Data_q(3 downto 0);
|
DAC_Val_UB <= Wr_Data_q(3 downto 0);
|
when "10" =>
|
when "10" =>
|
| Line 217... |
Line 226... |
DAC_Val <= DAC_Val_UB & DAC_Val_LB;
|
DAC_Val <= DAC_Val_UB & DAC_Val_LB;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
|
Rd_En_q <= Rd_En_d;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
if( Rd_En_q = '1' )then
|
if( Rd_En = '1' )then
|
case( Reg_Sel_q )is
|
case( Reg_Sel )is
|
|
when "00" =>
|
when "00" =>
|
Rd_Data <= DAC_Val_LB;
|
Rd_Data <= DAC_Val_LB;
|
when "01" =>
|
when "01" =>
|
Rd_Data <= x"0" & DAC_Val_UB;
|
Rd_Data <= x"0" & DAC_Val_UB;
|
when others => null;
|
when others => null;
|
