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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm12.vhd] - Diff between revs 244 and 268
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| Rev 244 |
Rev 268 |
| Line 41... |
Line 41... |
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_vdsm12 is
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entity o8_vdsm12 is
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generic(
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generic(
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Invert_Output : boolean := FALSE;
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Default_Value : std_logic_vector(11 downto 0) := x"000";
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Default_Value : std_logic_vector(11 downto 0) := x"000";
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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| Line 301... |
Line 303... |
end if;
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end if;
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Period_Ctr <= Period_Ctr - 1;
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Period_Ctr <= Period_Ctr - 1;
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Width_Ctr <= Width_Ctr - 1;
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Width_Ctr <= Width_Ctr - 1;
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DACOut <= '1';
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if( Invert_Output )then
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DACOut <= or_reduce(Width_Ctr);
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else
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DACOut <= nor_reduce(Width_Ctr);
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end if;
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if( Width_Ctr = 0 )then
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if( Width_Ctr = 0 )then
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DACOut <= '0';
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Width_Ctr <= (others => '0');
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Width_Ctr <= (others => '0');
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end if;
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end if;
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if( Period_Ctr = 0 )then
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if( Period_Ctr = 0 )then
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Period_Ctr <= PWM_Period;
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Period_Ctr <= PWM_Period;
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