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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm8.vhd] - Diff between revs 172 and 189

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Rev 172 Rev 189
Line 51... Line 51...
);
);
end entity;
end entity;
 
 
architecture behave of o8_vdsm8 is
architecture behave of o8_vdsm8 is
 
 
  function ceil_log2 (x : in natural) return natural is
 
    variable retval     : natural;
 
  begin
 
    retval              := 1;
 
    while ((2**retval) - 1) < x loop
 
      retval            := retval + 1;
 
    end loop;
 
    return retval;
 
  end function;
 
 
 
  constant User_Addr    : std_logic_vector(15 downto 0) := Address;
  constant User_Addr    : std_logic_vector(15 downto 0) := Address;
  alias  Comp_Addr      is Bus_Address(15 downto 0);
  alias  Comp_Addr      is Bus_Address(15 downto 0);
  signal Addr_Match     : std_logic;
  signal Addr_Match     : std_logic;
  signal Wr_En          : std_logic;
  signal Wr_En          : std_logic;
  signal Wr_Data_q      : DATA_TYPE;
  signal Wr_Data_q      : DATA_TYPE;

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