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-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- Copyright (c)2016, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_vdsm8
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-- VHDL Units : o8_vdsm8
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-- Description: 8-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
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-- Description: 8-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 06/23/16 Design start
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-- Seth Henry 04/10/20 Code Cleanup
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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architecture behave of o8_vdsm8 is
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architecture behave of o8_vdsm8 is
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic;
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic;
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signal Rd_En : std_logic := '0';
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signal DACin : DATA_TYPE;
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signal DACin : DATA_TYPE := x"00";
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-- DAC WIDTH = 8 is fixed, with all constants normalized
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-- DAC WIDTH = 8 is fixed, with all constants normalized
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-- against 256 (the MAX PERIOD)
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-- against 256 (the MAX PERIOD)
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constant DAC_WIDTH : integer := 8;
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constant DAC_WIDTH : integer := 8;
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_5 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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constant PADJ_6 : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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signal DACin_q : DATA_TYPE;
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signal DACin_q : DATA_TYPE := x"00";
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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(others => '0');
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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(others => '0');
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signal Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0) :=
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signal Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
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(others => '0');
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal diff : std_logic_vector(DIV_WIDTH downto 0) :=
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signal diff : std_logic_vector(DIV_WIDTH downto 0);
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(others => '0');
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constant CB : integer := ceil_log2(DIV_WIDTH);
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constant CB : integer := ceil_log2(DIV_WIDTH);
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signal count : std_logic_vector(CB-1 downto 0);
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signal count : std_logic_vector(CB-1 downto 0) :=
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(others => '0');
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signal Next_Width : DATA_TYPE;
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signal Next_Width : DATA_TYPE := x"00";
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signal Next_Period : DATA_TYPE;
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signal Next_Period : DATA_TYPE := x"00";
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signal PWM_Width : DATA_TYPE;
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signal PWM_Width : DATA_TYPE := x"00";
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signal PWM_Period : DATA_TYPE;
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signal PWM_Period : DATA_TYPE := x"00";
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signal Width_Ctr : DATA_TYPE;
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signal Width_Ctr : DATA_TYPE := x"00";
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signal Period_Ctr : DATA_TYPE;
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signal Period_Ctr : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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