| Line 22... |
Line 22... |
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_vdsm8
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-- VHDL Units : o8_vdsm8
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-- Description: 8-bit variable delta-sigma modulator.
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-- Description: 8-bit variable delta-sigma modulator.
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--
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--
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA DAC Value (RW)
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 06/23/16 Design start
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-- Seth Henry 06/23/16 Design start
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-- Seth Henry 04/10/20 Code Cleanup
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-- Seth Henry 04/10/20 Code Cleanup
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| Line 38... |
Line 42... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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|
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entity o8_vdsm8 is
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entity o8_vdsm8 is
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generic(
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generic(
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Default_Value : DATA_TYPE := x"00";
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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| Line 57... |
Line 62... |
);
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);
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end entity;
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end entity;
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architecture behave of o8_vdsm8 is
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architecture behave of o8_vdsm8 is
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0)
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:= Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE;
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signal Rd_En : std_logic := '0';
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signal Reg_Out : DATA_TYPE;
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signal DACin : DATA_TYPE := x"00";
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signal Rd_En : std_logic;
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begin
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begin
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|
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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|
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Reg_Out <= Default_Value;
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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DACin <= x"00";
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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DACin <= Wr_Data_q;
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Reg_Out <= Wr_Data_q;
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end if;
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end if;
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|
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= DACin;
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Rd_Data <= Reg_Out;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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|
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U_DAC : entity work.vdsm8
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U_DAC : entity work.vdsm8
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| Line 100... |
Line 105... |
Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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DACin => DACin,
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DACin => Reg_Out,
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DACout => DACout
|
DACout => DACout
|
);
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);
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|
|
end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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