| Line 50... |
Line 50... |
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
--
|
--
|
Bus_Address : in ADDRESS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Wr_Enable : in std_logic;
|
|
Wr_Data : in DATA_TYPE;
|
|
Rd_Enable : in std_logic;
|
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
--
|
--
|
DACout : out std_logic
|
DACout : out std_logic
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_vdsm8 is
|
architecture behave of o8_vdsm8 is
|
|
|
constant User_Addr : std_logic_vector(15 downto 0)
|
constant User_Addr : std_logic_vector(15 downto 0)
|
:= Address(15 downto 0);
|
:= Address(15 downto 0);
|
alias Comp_Addr is Bus_Address(15 downto 0);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
|
signal Addr_Match : std_logic;
|
signal Addr_Match : std_logic;
|
signal Wr_En : std_logic;
|
signal Wr_En : std_logic;
|
signal Wr_Data_q : DATA_TYPE;
|
signal Wr_Data_q : DATA_TYPE;
|
signal Reg_Out : DATA_TYPE;
|
signal Reg_Out : DATA_TYPE;
|
signal Rd_En : std_logic;
|
signal Rd_En : std_logic;
|
| Line 84... |
Line 81... |
Wr_Data_q <= x"00";
|
Wr_Data_q <= x"00";
|
Reg_Out <= Default_Value;
|
Reg_Out <= Default_Value;
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Open8_Bus.Wr_Data;
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
Reg_Out <= Wr_Data_q;
|
Reg_Out <= Wr_Data_q;
|
end if;
|
end if;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= Reg_Out;
|
Rd_Data <= Reg_Out;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
