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Line 75... |
constant User_Addr : std_logic_vector(15 downto 2) :=
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constant User_Addr : std_logic_vector(15 downto 2) :=
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Address(15 downto 2);
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Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate);
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constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate);
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-- Period of each bit in sub-clocks (subtract one to account for zero)
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-- Period of each bit in sub-clocks (subtract one to account for zero)
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constant Full_Per_i : integer := BAUD_RATE_DIV - 1;
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constant Full_Per_i : integer := BAUD_RATE_DIV - 1;
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Line 112... |
signal Rx_Valid : std_logic;
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signal Rx_Valid : std_logic;
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Reg_Sel_q <= (others => '0');
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Reg_Sel <= (others => '0');
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel_q <= Reg_Sel_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_q <= Rd_En_d;
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Reg_Sel <= Reg_Addr;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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Rd_Data <= Vector_Cmd;
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Rd_Data <= Vector_Cmd;
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when "01" =>
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when "01" =>
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Rd_Data <= Vector_Arg_LB;
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Rd_Data <= Vector_Arg_LB;
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when "10" =>
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when "10" =>
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