| Line 38... |
Line 38... |
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
|
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
|
-- change.
|
-- change.
|
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
|
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
|
-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
|
-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
|
-- conditions instead
|
-- conditions instead
|
|
-- Seth Henry 05/23/20 Added the parallel interface
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 60... |
Line 61... |
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
Interrupt : out std_logic;
|
Interrupt : out std_logic;
|
--
|
-- Parallel Interface
|
Rx_In : in std_logic
|
Vec_Req : in std_logic;
|
|
Vec_Index : in std_logic_vector(5 downto 0);
|
|
Vec_Data : in std_logic_vector(15 downto 0);
|
|
-- Serial Interface
|
|
Vec_Rx : in std_logic
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_vector_rx is
|
architecture behave of o8_vector_rx is
|
|
|
| Line 93... |
Line 98... |
|
|
signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0) :=
|
signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0) :=
|
(others => '0');
|
(others => '0');
|
signal Rx_Baud_Tick : std_logic;
|
signal Rx_Baud_Tick : std_logic;
|
|
|
signal Rx_In_SR : std_logic_vector(2 downto 0);
|
signal Vec_Rx_SR : std_logic_vector(2 downto 0);
|
alias Rx_In_MS is Rx_In_SR(2);
|
alias Vec_Rx_MS is Vec_Rx_SR(2);
|
signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
|
signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
|
signal RX_Idle : std_logic;
|
signal RX_Idle : std_logic;
|
|
signal Rx_Data : DATA_TYPE := x"00";
|
|
signal Rx_Valid : std_logic;
|
|
|
type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
|
type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
|
SEND_INTERRUPT );
|
SEND_INTERRUPT );
|
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
|
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
|
|
|
signal Vector_Cmd : DATA_TYPE := x"00";
|
signal Vec_Req_SR : std_logic_vector(2 downto 0);
|
signal Vector_Arg_LB : DATA_TYPE := x"00";
|
alias Vec_Req_MS is Vec_Rx_SR(2);
|
signal Vector_Arg_UB : DATA_TYPE := x"00";
|
|
|
|
signal Rx_Data : DATA_TYPE := x"00";
|
signal Vector_Index : DATA_TYPE := x"00";
|
signal Rx_Valid : std_logic;
|
signal Vector_Data : ADDRESS_TYPE := x"0000";
|
|
alias Vector_Data_LB is Vector_Data(7 downto 0);
|
|
alias Vector_Data_UB is Vector_Data(15 downto 8);
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
| Line 128... |
Line 136... |
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En_q <= Rd_En_d;
|
Rd_En_q <= Rd_En_d;
|
if( Rd_En_q = '1' )then
|
if( Rd_En_q = '1' )then
|
case( Reg_Sel_q )is
|
case( Reg_Sel_q )is
|
when "00" =>
|
when "00" =>
|
Rd_Data <= Vector_Cmd;
|
Rd_Data <= Vector_Index;
|
when "01" =>
|
when "01" =>
|
Rd_Data <= Vector_Arg_LB;
|
Rd_Data <= Vector_Data_LB;
|
when "10" =>
|
when "10" =>
|
Rd_Data <= Vector_Arg_UB;
|
Rd_Data <= Vector_Data_UB;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 145... |
Line 153... |
RX_Idle_proc: process( Clock, Reset )
|
RX_Idle_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Rx_Baud_Cntr <= (others => '0');
|
Rx_Baud_Cntr <= (others => '0');
|
Rx_Baud_Tick <= '0';
|
Rx_Baud_Tick <= '0';
|
Rx_In_SR <= (others => '1');
|
Vec_Rx_SR <= (others => '1');
|
Rx_Idle_Cntr <= (others => '0');
|
Rx_Idle_Cntr <= (others => '0');
|
Rx_Idle <= '0';
|
Rx_Idle <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1;
|
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1;
|
Rx_Baud_Tick <= '0';
|
Rx_Baud_Tick <= '0';
|
if( Rx_Baud_Cntr = 0 )then
|
if( Rx_Baud_Cntr = 0 )then
|
Rx_Baud_Cntr <= FULL_PERIOD;
|
Rx_Baud_Cntr <= FULL_PERIOD;
|
Rx_Baud_Tick <= '1';
|
Rx_Baud_Tick <= '1';
|
end if;
|
end if;
|
|
|
Rx_In_SR <= Rx_In_SR(1 downto 0) & Rx_In;
|
Vec_Rx_SR <= Vec_Rx_SR(1 downto 0) & Vec_Rx;
|
Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick;
|
Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick;
|
if( Rx_In_MS = '0' )then
|
if( Vec_Rx_MS = '0' )then
|
Rx_Idle_Cntr <= (others => '1');
|
Rx_Idle_Cntr <= (others => '1');
|
elsif( Rx_Idle_Cntr = 0 )then
|
elsif( Rx_Idle_Cntr = 0 )then
|
Rx_Idle_Cntr <= (others => '0');
|
Rx_Idle_Cntr <= (others => '0');
|
end if;
|
end if;
|
|
|
| Line 179... |
Line 187... |
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
Rx_In => RX_In,
|
RX_In => Vec_Rx,
|
--
|
--
|
Rx_Data => RX_Data,
|
Rx_Data => RX_Data,
|
Rx_Valid => RX_Valid,
|
Rx_Valid => RX_Valid,
|
Rx_PErr => open
|
Rx_PErr => open
|
);
|
);
|
|
|
Vector_RX_proc: process( Clock, Reset )
|
Vector_RX_proc: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
|
Vec_Req_SR <= (others => '0');
|
Vector_State <= GET_VECTOR_CMD;
|
Vector_State <= GET_VECTOR_CMD;
|
Vector_Cmd <= x"00";
|
Vector_Index <= x"00";
|
Vector_Arg_LB <= x"00";
|
Vector_Data <= x"0000";
|
Vector_Arg_UB <= x"00";
|
|
Interrupt <= '0';
|
Interrupt <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
|
Vec_Req_SR <= Vec_Req_SR(1 downto 0) & Vec_Req;
|
|
|
Interrupt <= '0';
|
Interrupt <= '0';
|
|
|
|
if( Vec_Req_MS = '1' )then
|
|
Vector_Index <= "00" & Vec_Index;
|
|
Vector_Data <= Vec_Data;
|
|
Interrupt <= '1';
|
|
end if;
|
|
|
case( Vector_State )is
|
case( Vector_State )is
|
when GET_VECTOR_CMD =>
|
when GET_VECTOR_CMD =>
|
if( Rx_Valid = '1' )then
|
if( Rx_Valid = '1' )then
|
Vector_Cmd <= Rx_Data;
|
Vector_Index <= "00" & Rx_Data(5 downto 0);
|
Vector_State <= GET_VECTOR_ARG_LB;
|
Vector_State <= GET_VECTOR_ARG_LB;
|
end if;
|
end if;
|
|
|
when GET_VECTOR_ARG_LB =>
|
when GET_VECTOR_ARG_LB =>
|
if( Rx_Valid = '1' )then
|
if( Rx_Valid = '1' )then
|
Vector_Arg_LB <= Rx_Data;
|
Vector_Data_LB <= Rx_Data;
|
Vector_State <= GET_VECTOR_ARG_UB;
|
Vector_State <= GET_VECTOR_ARG_UB;
|
end if;
|
end if;
|
|
|
when GET_VECTOR_ARG_UB =>
|
when GET_VECTOR_ARG_UB =>
|
if( Rx_Valid = '1' )then
|
if( Rx_Valid = '1' )then
|
Vector_Arg_UB <= Rx_Data;
|
Vector_Data_UB <= Rx_Data;
|
Vector_State <= SEND_INTERRUPT;
|
Vector_State <= SEND_INTERRUPT;
|
end if;
|
end if;
|
|
|
when SEND_INTERRUPT =>
|
when SEND_INTERRUPT =>
|
Interrupt <= '1';
|
Interrupt <= '1';
|
