URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vector_rx.vhd] - Diff between revs 246 and 247
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 246 |
Rev 247 |
| Line 110... |
Line 110... |
type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
|
type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
|
SEND_INTERRUPT );
|
SEND_INTERRUPT );
|
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
|
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
|
|
|
signal Vec_Req_SR : std_logic_vector(2 downto 0);
|
signal Vec_Req_SR : std_logic_vector(2 downto 0);
|
alias Vec_Req_MS is Vec_Rx_SR(2);
|
alias Vec_Req_MS is Vec_Req_SR(2);
|
|
|
signal Vector_Index : DATA_TYPE := x"00";
|
signal Vector_Index : DATA_TYPE := x"00";
|
signal Vector_Data : ADDRESS_TYPE := x"0000";
|
signal Vector_Data : ADDRESS_TYPE := x"0000";
|
alias Vector_Data_LB is Vector_Data(7 downto 0);
|
alias Vector_Data_LB is Vector_Data(7 downto 0);
|
alias Vector_Data_UB is Vector_Data(15 downto 8);
|
alias Vector_Data_UB is Vector_Data(15 downto 8);
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.