| Line 39... |
Line 39... |
-- change.
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-- change.
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
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-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
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-- conditions instead
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-- conditions instead
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-- Seth Henry 05/23/20 Added the parallel interface
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-- Seth Henry 05/23/20 Added the parallel interface
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-- Seth Henry 04/07/21 Added checksum to prevent glitching on serial noise
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 105... |
Line 106... |
signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
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signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
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signal RX_Idle : std_logic;
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signal RX_Idle : std_logic;
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signal Rx_Data : DATA_TYPE := x"00";
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signal Rx_Data : DATA_TYPE := x"00";
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signal Rx_Valid : std_logic;
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signal Rx_Valid : std_logic;
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type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
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type VECTOR_RX_STATES is ( CHECKSUM_INIT,
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GET_VECTOR_CMD,
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GET_VECTOR_ARG_LB,
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GET_VECTOR_ARG_UB,
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GET_VECTOR_SUM,
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SEND_INTERRUPT );
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SEND_INTERRUPT );
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signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
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signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
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signal Vec_Req_SR : std_logic_vector(2 downto 0);
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signal Vec_Req_SR : std_logic_vector(2 downto 0);
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alias Vec_Req_MS is Vec_Req_SR(2);
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alias Vec_Req_MS is Vec_Req_SR(2);
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signal Vector_Index : DATA_TYPE := x"00";
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signal Vector_Index : DATA_TYPE := x"00";
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signal Vector_Data : ADDRESS_TYPE := x"0000";
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signal Vector_Data : ADDRESS_TYPE := x"0000";
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alias Vector_Data_LB is Vector_Data(7 downto 0);
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alias Vector_Data_LB is Vector_Data(7 downto 0);
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alias Vector_Data_UB is Vector_Data(15 downto 8);
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alias Vector_Data_UB is Vector_Data(15 downto 8);
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signal Vector_RX_Sum : DATA_TYPE := x"00";
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constant MAGIC_NUM : DATA_TYPE := x"4D";
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signal Checksum : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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| Line 198... |
Line 207... |
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Vector_RX_proc: process( Clock, Reset )
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Vector_RX_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Vec_Req_SR <= (others => '0');
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Vec_Req_SR <= (others => '0');
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Vector_State <= GET_VECTOR_CMD;
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Vector_State <= CHECKSUM_INIT;
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Vector_Index <= x"00";
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Vector_Index <= x"00";
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Vector_Data <= x"0000";
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Vector_Data <= x"0000";
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Vec_Req_SR <= Vec_Req_SR(1 downto 0) & Vec_Req;
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Vec_Req_SR <= Vec_Req_SR(1 downto 0) & Vec_Req;
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| Line 214... |
Line 223... |
Vector_Data <= Vec_Data;
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Vector_Data <= Vec_Data;
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Interrupt <= '1';
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Interrupt <= '1';
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end if;
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end if;
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case( Vector_State )is
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case( Vector_State )is
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when CHECKSUM_INIT =>
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Checksum <= MAGIC_NUM;
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Vector_State <= GET_VECTOR_CMD;
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when GET_VECTOR_CMD =>
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when GET_VECTOR_CMD =>
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if( Rx_Valid = '1' )then
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if( Rx_Valid = '1' )then
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Checksum <= Checksum + Rx_Data;
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Vector_Index <= "00" & Rx_Data(5 downto 0);
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Vector_Index <= "00" & Rx_Data(5 downto 0);
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Vector_State <= GET_VECTOR_ARG_LB;
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Vector_State <= GET_VECTOR_ARG_LB;
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end if;
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end if;
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when GET_VECTOR_ARG_LB =>
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when GET_VECTOR_ARG_LB =>
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if( Rx_Valid = '1' )then
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if( Rx_Valid = '1' )then
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Checksum <= Checksum + Rx_Data;
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Vector_Data_LB <= Rx_Data;
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Vector_Data_LB <= Rx_Data;
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Vector_State <= GET_VECTOR_ARG_UB;
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Vector_State <= GET_VECTOR_ARG_UB;
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end if;
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end if;
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when GET_VECTOR_ARG_UB =>
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when GET_VECTOR_ARG_UB =>
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if( Rx_Valid = '1' )then
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if( Rx_Valid = '1' )then
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Checksum <= Checksum + Rx_Data;
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Vector_Data_UB <= Rx_Data;
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Vector_Data_UB <= Rx_Data;
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Vector_State <= GET_VECTOR_SUM;
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end if;
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when GET_VECTOR_SUM =>
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if( Rx_Valid = '1' )then
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Vector_RX_Sum <= Rx_Data;
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Vector_State <= SEND_INTERRUPT;
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Vector_State <= SEND_INTERRUPT;
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end if;
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end if;
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when SEND_INTERRUPT =>
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when SEND_INTERRUPT =>
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if( Checksum = Vector_RX_Sum )then
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Interrupt <= '1';
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Interrupt <= '1';
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Vector_State <= GET_VECTOR_CMD;
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end if;
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Vector_State <= CHECKSUM_INIT;
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when others => null;
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when others => null;
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end case;
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end case;
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if( Rx_Idle = '1' )then
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if( Rx_Idle = '1' )then
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Vector_State <= GET_VECTOR_CMD;
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Vector_State <= CHECKSUM_INIT;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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