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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_crc16_ccitt.vhd] - Diff between revs 191 and 202
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| Rev 191 |
Rev 202 |
| Line 39... |
Line 39... |
port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Clear : in std_logic;
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Clear : in std_logic;
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Wr_Data : in DATA_IN_TYPE;
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Wr_En : in std_logic;
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Wr_En : in std_logic;
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Wr_Data : in DATA_IN_TYPE;
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--
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--
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CRC16_Out : out CRC_OUT_TYPE;
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CRC16_Valid : out std_logic;
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CRC16_Valid : out std_logic
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CRC16_Out : out CRC_OUT_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of sdlc_crc16_ccitt is
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architecture behave of sdlc_crc16_ccitt is
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| Line 98... |
Line 98... |
Reg(11) <= Exr(3) ;
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Reg(11) <= Exr(3) ;
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Reg(12) <= Exr(4) xor Exr(0);
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Reg(12) <= Exr(4) xor Exr(0);
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Reg(13) <= Exr(5) xor Exr(1);
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Reg(13) <= Exr(5) xor Exr(1);
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Reg(14) <= Exr(6) xor Exr(2);
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Reg(14) <= Exr(6) xor Exr(2);
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Reg(15) <= Exr(7) xor Exr(3);
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Reg(15) <= Exr(7) xor Exr(3);
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elsif( Clear = '1' )then
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end if;
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if( Clear = '1' )then
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Reg <= Poly_Init;
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Reg <= Poly_Init;
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end if;
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end if;
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Buffer_En <= Calc_En;
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Buffer_En <= Calc_En;
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if( Buffer_En = '1' )then
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if( Buffer_En = '1' )then
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