URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_crc16_ccitt.vhd] - Diff between revs 191 and 202

Rev 191	Rev 202
Line 39...	Line 39...
`port(`	`port(`
`Clock : in std_logic;`	`Clock : in std_logic;`
`Reset : in std_logic;`	`Reset : in std_logic;`
`--`	`--`
`Clear : in std_logic;`	`Clear : in std_logic;`
`Wr_Data : in DATA_IN_TYPE;`
`Wr_En : in std_logic;`	`Wr_En : in std_logic;`
	`Wr_Data : in DATA_IN_TYPE;`
`--`	`--`
`CRC16_Out : out CRC_OUT_TYPE;`	`CRC16_Valid : out std_logic;`
`CRC16_Valid : out std_logic`	`CRC16_Out : out CRC_OUT_TYPE`
`);`	`);`
`end entity;`	`end entity;`

`architecture behave of sdlc_crc16_ccitt is`	`architecture behave of sdlc_crc16_ccitt is`

Line 98...	Line 98...
`Reg(11) <= Exr(3) ;`	`Reg(11) <= Exr(3) ;`
`Reg(12) <= Exr(4) xor Exr(0);`	`Reg(12) <= Exr(4) xor Exr(0);`
`Reg(13) <= Exr(5) xor Exr(1);`	`Reg(13) <= Exr(5) xor Exr(1);`
`Reg(14) <= Exr(6) xor Exr(2);`	`Reg(14) <= Exr(6) xor Exr(2);`
`Reg(15) <= Exr(7) xor Exr(3);`	`Reg(15) <= Exr(7) xor Exr(3);`
`elsif( Clear = '1' )then`	`end if;`

	`if( Clear = '1' )then`
`Reg <= Poly_Init;`	`Reg <= Poly_Init;`
`end if;`	`end if;`

`Buffer_En <= Calc_En;`	`Buffer_En <= Calc_En;`
`if( Buffer_En = '1' )then`	`if( Buffer_En = '1' )then`