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[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_crc16_ccitt.vhd] - Diff between revs 202 and 205
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Rev 205 |
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Line 49... |
);
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);
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end entity;
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end entity;
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architecture behave of sdlc_crc16_ccitt is
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architecture behave of sdlc_crc16_ccitt is
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signal Calc_En : std_logic;
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signal Calc_En : std_logic := '0';
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signal Buffer_En : std_logic;
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signal Buffer_En : std_logic := '0';
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signal Data : DATA_IN_TYPE;
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signal Data : DATA_IN_TYPE := x"00";
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signal Exr : DATA_IN_TYPE;
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signal Exr : DATA_IN_TYPE := x"00";
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signal Reg : CRC_OUT_TYPE;
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signal Reg : CRC_OUT_TYPE := x"0000";
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begin
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begin
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Exr(0) <= Reg(0) xor Data(0);
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Exr(0) <= Reg(0) xor Data(0);
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Exr(1) <= Reg(1) xor Data(1);
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Exr(1) <= Reg(1) xor Data(1);
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