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[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_crc16_ccitt.vhd] - Diff between revs 220 and 265

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Rev 220 Rev 265
Line 77... Line 77...
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Calc_En                <= '0';
      Calc_En                <= '0';
      Buffer_En              <= '0';
      Buffer_En              <= '0';
      Data                   <= x"00";
      Data                   <= x"00";
      Reg                    <= x"0000";
      Reg                    <= Poly_Init;
      CRC16_Out              <= x"0000";
      CRC16_Out              <= x"0000";
      CRC16_Valid            <= '0';
      CRC16_Valid            <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Calc_En                <= Wr_En;
      Calc_En                <= Wr_En;
      if( Wr_En  = '1' )then
      if( Wr_En  = '1' )then

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