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[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_crc16_ccitt.vhd] - Diff between revs 220 and 265
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| Rev 220 |
Rev 265 |
| Line 77... |
Line 77... |
begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Calc_En <= '0';
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Calc_En <= '0';
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Buffer_En <= '0';
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Buffer_En <= '0';
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Data <= x"00";
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Data <= x"00";
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Reg <= x"0000";
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Reg <= Poly_Init;
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CRC16_Out <= x"0000";
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CRC16_Out <= x"0000";
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CRC16_Valid <= '0';
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CRC16_Valid <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Calc_En <= Wr_En;
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Calc_En <= Wr_En;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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