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[/] [open8_urisc/] [trunk/] [VHDL/] [vdsm8.vhd] - Diff between revs 218 and 219
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-- Copyright (c)2020 Jeremy Seth Henry
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-- Copyright (c)2018, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : vdsm8
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-- VHDL Units : vdsm8
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-- Description: 8-bit variable delta-sigma modulator single-bit DAC
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-- Description: 8-bit variable delta-sigma modulator single-bit DAC
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/25/18 Initial design
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-- Seth Henry 04/14/20 Code cleanup and revision section added
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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