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[/] [open8_urisc/] [trunk/] [VHDL/] [vector_tx.vhd] - Diff between revs 268 and 285

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Rev 268 Rev 285
Line 28... Line 28...
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      05/06/20 Added version block
-- Seth Henry      05/06/20 Added version block
 
-- Seth Henry      04/07/21 Modified to replace hard-coded blocks with true
 
--                           argument inputs.
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_misc.all;
  use ieee.std_logic_misc.all;
 
 
 
library work;
 
  use work.open8_pkg.all;
 
 
entity vector_tx is
entity vector_tx is
generic(
generic(
  Button_Level               : std_logic;
  Button_Level               : std_logic;
  Bit_Rate                   : real;
  Bit_Rate                   : real;
  Enable_Parity              : boolean;
  Enable_Parity              : boolean;
Line 48... Line 53...
);
);
port(
port(
  Clock                      : in  std_logic;
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  Reset                      : in  std_logic;
  --
  --
  Switches                   : in  std_logic_vector(9 downto 0);
  Tx_Enable                  : in  std_logic;
  Pushbutton                 : in  std_logic;
  Tx_Command                 : in  DATA_TYPE;
 
  Tx_Arg_Lower               : in  DATA_TYPE;
 
  Tx_Arg_Upper               : in  DATA_TYPE;
 
  --
 
  Tx_Busy                    : out std_logic;
  --
  --
  Tx_Out                     : out std_logic
  Tx_Out                     : out std_logic;
 
  Tx_FC                      : in  std_logic := '1'
);
);
end entity;
end entity;
 
 
architecture behave of vector_tx is
architecture behave of vector_tx is
 
 
  signal uSec_Tick           : std_logic;
  signal Command_Buffer      : DATA_TYPE := x"00";
  signal mSec_Tick           : std_logic;
  signal Arg_Lower_Buffer    : DATA_TYPE := x"00";
 
  signal Arg_Upper_Buffer    : DATA_TYPE := x"00";
  signal Button_Pressed      : std_logic := '0';
 
  signal Button_CoS          : std_logic := '0';
  type VECTOR_TX_STATES is (IDLE,
 
                            SEND_CMD, WAIT_CMD,
  type VEC_ARG_TYPE is array(0 to 31) of std_logic_vector(15 downto 0);
                            SEND_ARG_LB, WAIT_ARG_LB,
  constant VEC_ARGS          : VEC_ARG_TYPE := (
                            SEND_ARG_UB, WAIT_ARG_UB,
                               x"0000",
                            SEND_SUM, WAIT_SUM );
                               x"0001",
 
                               x"0002",
 
                               x"0003",
 
                               x"0004",
 
                               x"0005",
 
                               x"0006",
 
                               x"0007",
 
                               x"0008",
 
                               x"0009",
 
                               x"000A",
 
                               x"000B",
 
                               x"000C",
 
                               x"000D",
 
                               x"000E",
 
                               x"000F",
 
 
 
                               x"0800",
 
                               x"0866",
 
                               x"0975",
 
                               x"00AE",
 
                               x"DEAD",
 
                               x"BEEF",
 
                               x"CAFE",
 
                               x"BABE",
 
                               x"DECA",
 
                               x"A5A5",
 
                               x"C3C3",
 
                               x"0123",
 
                               x"4567",
 
                               x"89AB",
 
                               x"CDEF",
 
                               x"FFFF"
 
                             );
 
 
 
  alias Vector_Arg_Sel       is Switches(9 downto 5);
 
  alias Vector_Cmd_Sel       is Switches(4 downto 0);
 
 
 
  signal Vector_Cmd          : std_logic_vector(7 downto 0);
 
 
 
  signal Vector_Arg          : std_logic_vector(15 downto 0);
 
  alias Vector_Arg_LB        is Vector_Arg(7 downto 0);
 
  alias Vector_Arg_UB        is Vector_Arg(15 downto 8);
 
 
 
  type VECTOR_TX_STATES is (IDLE, SEND_CMD, WAIT_CMD, SEND_ARG_LB, WAIT_ARG_LB, SEND_ARG_UB, WAIT_ARG_UB );
 
  signal Vector_State        : VECTOR_TX_STATES := IDLE;
  signal Vector_State        : VECTOR_TX_STATES := IDLE;
 
 
  constant BAUD_RATE_DIV     : integer := integer(Sys_Freq / Bit_Rate);
  constant BAUD_RATE_DIV     : integer := integer(Sys_Freq / Bit_Rate);
 
 
  signal Tx_Data             : std_logic_vector(7 downto 0) := x"00";
  constant MAGIC_NUM         : DATA_TYPE := x"4D";
 
  signal Checksum            : DATA_TYPE := x"00";
 
 
 
  signal Tx_Data             : DATA_TYPE := x"00";
  signal Tx_Valid            : std_logic := '0';
  signal Tx_Valid            : std_logic := '0';
  signal Tx_Done             : std_logic := '0';
  signal Tx_Done             : std_logic := '0';
 
 
begin
begin
 
 
  U_USEC : entity work.sys_tick
 
  generic map(
 
    Reset_Level              => Reset_Level,
 
    Sys_Freq                 => Sys_Freq
 
  )
 
  port map(
 
    Clock                    => Clock,
 
    Reset                    => Reset,
 
    uSec_Tick                => uSec_Tick,
 
    mSec_Tick                => mSec_Tick
 
  );
 
 
 
  U_BTN : entity work.button_db
 
  generic map(
 
    Button_Level             => Button_Level,
 
    Reset_Level              => Reset_Level
 
  )
 
  port map(
 
    Clock                    => Clock,
 
    Reset                    => Reset,
 
    mSec_Tick                => mSec_Tick,
 
    --
 
    Button_In                => Pushbutton,
 
    --
 
    Button_Pressed           => Button_Pressed,
 
    Button_CoS               => Button_CoS
 
  );
 
 
 
  Input_reg_proc: process( Clock, Reset )
 
  begin
 
    if( Reset = Reset_Level )then
 
      Vector_Cmd             <= x"00";
 
      Vector_Arg             <= x"0000";
 
    elsif( rising_edge(Clock) )then
 
      Vector_Cmd             <= "000" & Vector_Cmd_Sel;
 
      Vector_Arg             <= VEC_ARGS(conv_integer(Vector_Arg_Sel));
 
    end if;
 
  end process;
 
 
 
  TX_FSM_proc: process( Clock, Reset )
  TX_FSM_proc: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Vector_State           <= IDLE;
      Vector_State           <= IDLE;
 
      Command_Buffer         <= x"00";
 
      Arg_Lower_Buffer       <= x"00";
 
      Arg_Upper_Buffer       <= x"00";
 
      Tx_Busy                <= '0';
      Tx_Data                <= x"00";
      Tx_Data                <= x"00";
      Tx_Valid               <= '0';
      Tx_Valid               <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
 
      Tx_Busy                <= '1';
      Tx_Data                <= x"00";
      Tx_Data                <= x"00";
      Tx_Valid               <= '0';
      Tx_Valid               <= '0';
      case( Vector_State )is
      case( Vector_State )is
        when IDLE =>
        when IDLE =>
          if( Button_CoS = '1' and Button_Pressed = '1' )then
          Tx_Busy            <= '0';
 
          Checksum           <= MAGIC_NUM;
 
          if( Tx_Enable = '1' )then
 
            Command_Buffer   <= Tx_Command;
 
            Arg_Lower_Buffer <= Tx_Arg_Lower;
 
            Arg_Upper_Buffer <= Tx_Arg_Upper;
            Vector_State     <= SEND_CMD;
            Vector_State     <= SEND_CMD;
          end if;
          end if;
 
 
        when SEND_CMD =>
        when SEND_CMD =>
          Tx_Data            <= Vector_Cmd;
          Tx_Data            <= Command_Buffer;
          Tx_Valid           <= '1';
          Tx_Valid           <= '1';
 
          Checksum           <= Checksum + Command_Buffer;
          Vector_State       <= WAIT_CMD;
          Vector_State       <= WAIT_CMD;
 
 
        when WAIT_CMD =>
        when WAIT_CMD =>
          if( Tx_Done = '1' )then
          if( Tx_Done = '1' )then
            Vector_State     <= SEND_ARG_LB;
            Vector_State     <= SEND_ARG_LB;
          end if;
          end if;
 
 
        when SEND_ARG_LB =>
        when SEND_ARG_LB =>
          Tx_Data            <= Vector_Arg_LB;
          Tx_Data            <= Arg_Lower_Buffer;
          Tx_Valid           <= '1';
          Tx_Valid           <= '1';
 
          Checksum           <= Checksum + Arg_Lower_Buffer;
          Vector_State       <= WAIT_ARG_LB;
          Vector_State       <= WAIT_ARG_LB;
 
 
        when WAIT_ARG_LB =>
        when WAIT_ARG_LB =>
          if( Tx_Done = '1' )then
          if( Tx_Done = '1' )then
            Vector_State     <= SEND_ARG_UB;
            Vector_State     <= SEND_ARG_UB;
          end if;
          end if;
 
 
        when SEND_ARG_UB =>
        when SEND_ARG_UB =>
          Tx_Data            <= Vector_Arg_UB;
          Tx_Data            <= Arg_Upper_Buffer;
          Tx_Valid           <= '1';
          Tx_Valid           <= '1';
 
          Checksum           <= Checksum + Arg_Upper_Buffer;
          Vector_State       <= WAIT_ARG_UB;
          Vector_State       <= WAIT_ARG_UB;
 
 
        when WAIT_ARG_UB =>
        when WAIT_ARG_UB =>
          if( Tx_Done = '1' )then
          if( Tx_Done = '1' )then
 
            Vector_State     <= SEND_SUM;
 
          end if;
 
 
 
        when SEND_SUM =>
 
          Tx_Data            <= Checksum;
 
          Tx_Valid           <= '1';
 
          Vector_State       <= WAIT_SUM;
 
 
 
        when WAIT_SUM =>
 
          if( Tx_Done = '1' )then
            Vector_State     <= IDLE;
            Vector_State     <= IDLE;
          end if;
          end if;
 
 
      end case;
      end case;
    end if;
    end if;

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