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[/] [open8_urisc/] [trunk/] [VHDL/] [vector_tx.vhd] - Diff between revs 285 and 296

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Rev 285 Rev 296
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-- Copyright (c)2020 Jeremy Seth Henry
-- Copyright (c)2021 Jeremy Seth Henry
-- All rights reserved.
-- All rights reserved.
--
--
-- Redistribution and use in source and binary forms, with or without
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--     * Redistributions of source code must retain the above copyright
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-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      05/06/20 Added version block
-- Seth Henry      05/06/20 Added version block
-- Seth Henry      04/07/21 Modified to replace hard-coded blocks with true
-- Seth Henry      04/07/21 Modified to replace hard-coded blocks with true
--                           argument inputs.
--                           argument inputs.
 
-- Seth Henry      09/15/21 Added flow control and made the Magic_Num a generic
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
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library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity vector_tx is
entity vector_tx is
generic(
generic(
  Button_Level               : std_logic;
  Magic_Num                  : DATA_TYPE := x"4D";
  Bit_Rate                   : real;
  Bit_Rate                   : real;
  Enable_Parity              : boolean;
  Enable_Parity              : boolean;
  Parity_Odd_Even_n          : std_logic;
  Parity_Odd_Even_n          : std_logic;
  Sys_Freq                   : real;
  Clock_Frequency            : real;
  Reset_Level                : std_logic
  Reset_Level                : std_logic
);
);
port(
port(
  Clock                      : in  std_logic;
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  Reset                      : in  std_logic;
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  signal Command_Buffer      : DATA_TYPE := x"00";
  signal Command_Buffer      : DATA_TYPE := x"00";
  signal Arg_Lower_Buffer    : DATA_TYPE := x"00";
  signal Arg_Lower_Buffer    : DATA_TYPE := x"00";
  signal Arg_Upper_Buffer    : DATA_TYPE := x"00";
  signal Arg_Upper_Buffer    : DATA_TYPE := x"00";
 
 
  type VECTOR_TX_STATES is (IDLE,
  type VECTOR_TX_STATES is (IDLE, WAIT_FC,
                            SEND_CMD, WAIT_CMD,
                            SEND_CMD, WAIT_CMD,
                            SEND_ARG_LB, WAIT_ARG_LB,
                            SEND_ARG_LB, WAIT_ARG_LB,
                            SEND_ARG_UB, WAIT_ARG_UB,
                            SEND_ARG_UB, WAIT_ARG_UB,
                            SEND_SUM, WAIT_SUM );
                            SEND_SUM_LB, WAIT_SUM_LB,
 
                            SEND_SUM_UB, WAIT_SUM_UB );
  signal Vector_State        : VECTOR_TX_STATES := IDLE;
  signal Vector_State        : VECTOR_TX_STATES := IDLE;
 
 
  constant BAUD_RATE_DIV     : integer := integer(Sys_Freq / Bit_Rate);
  constant BAUD_RATE_DIV     : integer := integer(Clock_Frequency / Bit_Rate);
 
 
  constant MAGIC_NUM         : DATA_TYPE := x"4D";
  signal Checksum            : ADDRESS_TYPE := x"0000";
  signal Checksum            : DATA_TYPE := x"00";
  alias  Checksum_LB         is Checksum(7 downto 0);
 
  alias  Checksum_UB         is Checksum(15 downto 8);
 
 
  signal Tx_Data             : DATA_TYPE := x"00";
  signal Tx_Data             : DATA_TYPE := x"00";
  signal Tx_Valid            : std_logic := '0';
  signal Tx_Valid            : std_logic := '0';
  signal Tx_Done             : std_logic := '0';
  signal Tx_Done             : std_logic := '0';
 
 
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      Tx_Data                <= x"00";
      Tx_Data                <= x"00";
      Tx_Valid               <= '0';
      Tx_Valid               <= '0';
      case( Vector_State )is
      case( Vector_State )is
        when IDLE =>
        when IDLE =>
          Tx_Busy            <= '0';
          Tx_Busy            <= '0';
          Checksum           <= MAGIC_NUM;
          Checksum           <= x"00" & MAGIC_NUM;
          if( Tx_Enable = '1' )then
          if( Tx_Enable = '1' )then
            Command_Buffer   <= Tx_Command;
            Command_Buffer   <= Tx_Command;
            Arg_Lower_Buffer <= Tx_Arg_Lower;
            Arg_Lower_Buffer <= Tx_Arg_Lower;
            Arg_Upper_Buffer <= Tx_Arg_Upper;
            Arg_Upper_Buffer <= Tx_Arg_Upper;
 
            Vector_State     <= WAIT_FC;
 
          end if;
 
 
 
        when WAIT_FC =>
 
          if( Tx_FC = '1' )then
            Vector_State     <= SEND_CMD;
            Vector_State     <= SEND_CMD;
          end if;
          end if;
 
 
        when SEND_CMD =>
        when SEND_CMD =>
          Tx_Data            <= Command_Buffer;
          Tx_Data            <= Command_Buffer;
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          Checksum           <= Checksum + Arg_Upper_Buffer;
          Checksum           <= Checksum + Arg_Upper_Buffer;
          Vector_State       <= WAIT_ARG_UB;
          Vector_State       <= WAIT_ARG_UB;
 
 
        when WAIT_ARG_UB =>
        when WAIT_ARG_UB =>
          if( Tx_Done = '1' )then
          if( Tx_Done = '1' )then
            Vector_State     <= SEND_SUM;
            Vector_State     <= SEND_SUM_LB;
 
          end if;
 
 
 
        when SEND_SUM_LB =>
 
          Tx_Data            <= Checksum_LB;
 
          Tx_Valid           <= '1';
 
          Vector_State       <= WAIT_SUM_LB;
 
 
 
        when WAIT_SUM_LB =>
 
          if( Tx_Done = '1' )then
 
            Vector_State     <= SEND_SUM_UB;
          end if;
          end if;
 
 
        when SEND_SUM =>
        when SEND_SUM_UB =>
          Tx_Data            <= Checksum;
          Tx_Data            <= Checksum_UB;
          Tx_Valid           <= '1';
          Tx_Valid           <= '1';
          Vector_State       <= WAIT_SUM;
          Vector_State       <= WAIT_SUM_UB;
 
 
        when WAIT_SUM =>
        when WAIT_SUM_UB =>
          if( Tx_Done = '1' )then
          if( Tx_Done = '1' )then
            Vector_State     <= IDLE;
            Vector_State     <= IDLE;
          end if;
          end if;
 
 
      end case;
      end case;

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