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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [bfd/] [bfd-in2.h] - Diff between revs 163 and 166

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Rev 163 Rev 166
Line 1880... Line 1880...
#define bfd_mach_mips_loongson_2e      3001
#define bfd_mach_mips_loongson_2e      3001
#define bfd_mach_mips_loongson_2f      3002
#define bfd_mach_mips_loongson_2f      3002
#define bfd_mach_mips_loongson_3a      3003
#define bfd_mach_mips_loongson_3a      3003
#define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon           6501
#define bfd_mach_mips_octeon           6501
 
#define bfd_mach_mips_octeonp          6601
 
#define bfd_mach_mips_octeon2          6502
#define bfd_mach_mips_xlr              887682   /* decimal 'XLR'  */
#define bfd_mach_mips_xlr              887682   /* decimal 'XLR'  */
#define bfd_mach_mipsisa32             32
#define bfd_mach_mipsisa32             32
#define bfd_mach_mipsisa32r2           33
#define bfd_mach_mipsisa32r2           33
#define bfd_mach_mipsisa64             64
#define bfd_mach_mipsisa64             64
#define bfd_mach_mipsisa64r2           65
#define bfd_mach_mipsisa64r2           65
Line 2155... Line 2157...
  bfd_arch_microblaze,/* Xilinx MicroBlaze. */
  bfd_arch_microblaze,/* Xilinx MicroBlaze. */
  bfd_arch_tilepro,   /* Tilera TILEPro */
  bfd_arch_tilepro,   /* Tilera TILEPro */
  bfd_arch_tilegx, /* Tilera TILE-Gx */
  bfd_arch_tilegx, /* Tilera TILE-Gx */
#define bfd_mach_tilepro   1
#define bfd_mach_tilepro   1
#define bfd_mach_tilegx    1
#define bfd_mach_tilegx    1
 
#define bfd_mach_tilegx32  2
  bfd_arch_open8,       /* Open8/ARClite/V8 microcontrollers.  */
  bfd_arch_open8,       /* Open8/ARClite/V8 microcontrollers.  */
#define bfd_mach_open8_1               1
#define bfd_mach_open8_1               1
  bfd_arch_last
  bfd_arch_last
  };
  };
 
 
Line 2179... Line 2182...
  const struct bfd_arch_info * (*compatible)
  const struct bfd_arch_info * (*compatible)
    (const struct bfd_arch_info *a, const struct bfd_arch_info *b);
    (const struct bfd_arch_info *a, const struct bfd_arch_info *b);
 
 
  bfd_boolean (*scan) (const struct bfd_arch_info *, const char *);
  bfd_boolean (*scan) (const struct bfd_arch_info *, const char *);
 
 
 
  /* Allocate via bfd_malloc and return a fill buffer of size COUNT.  If
 
     IS_BIGENDIAN is TRUE, the order of bytes is big endian.  If CODE is
 
     TRUE, the buffer contains code.  */
 
  void *(*fill) (bfd_size_type count, bfd_boolean is_bigendian,
 
                 bfd_boolean code);
 
 
  const struct bfd_arch_info *next;
  const struct bfd_arch_info *next;
}
}
bfd_arch_info_type;
bfd_arch_info_type;
 
 
const char *bfd_printable_name (bfd *abfd);
const char *bfd_printable_name (bfd *abfd);
Line 2784... Line 2793...
  BFD_RELOC_MIPS16_HI16_S,
  BFD_RELOC_MIPS16_HI16_S,
 
 
/* MIPS16 low 16 bits.  */
/* MIPS16 low 16 bits.  */
  BFD_RELOC_MIPS16_LO16,
  BFD_RELOC_MIPS16_LO16,
 
 
 
/* MIPS16 TLS relocations  */
 
  BFD_RELOC_MIPS16_TLS_GD,
 
  BFD_RELOC_MIPS16_TLS_LDM,
 
  BFD_RELOC_MIPS16_TLS_DTPREL_HI16,
 
  BFD_RELOC_MIPS16_TLS_DTPREL_LO16,
 
  BFD_RELOC_MIPS16_TLS_GOTTPREL,
 
  BFD_RELOC_MIPS16_TLS_TPREL_HI16,
 
  BFD_RELOC_MIPS16_TLS_TPREL_LO16,
 
 
/* Relocation against a MIPS literal section.  */
/* Relocation against a MIPS literal section.  */
  BFD_RELOC_MIPS_LITERAL,
  BFD_RELOC_MIPS_LITERAL,
  BFD_RELOC_MICROMIPS_LITERAL,
  BFD_RELOC_MICROMIPS_LITERAL,
 
 
/* microMIPS PC-relative relocations.  */
/* microMIPS PC-relative relocations.  */
Line 4834... Line 4852...
 
 
/* Difference between two section addreses.  Must be followed by a
/* Difference between two section addreses.  Must be followed by a
BFD_RELOC_MACH_O_PAIR.  */
BFD_RELOC_MACH_O_PAIR.  */
  BFD_RELOC_MACH_O_SECTDIFF,
  BFD_RELOC_MACH_O_SECTDIFF,
 
 
 
/* Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.  */
 
  BFD_RELOC_MACH_O_LOCAL_SECTDIFF,
 
 
/* Pair of relocation.  Contains the first symbol.  */
/* Pair of relocation.  Contains the first symbol.  */
  BFD_RELOC_MACH_O_PAIR,
  BFD_RELOC_MACH_O_PAIR,
 
 
/* PCREL relocations.  They are marked as branch to create PLT entry if
/* PCREL relocations.  They are marked as branch to create PLT entry if
required.  */
required.  */
Line 4964... Line 4985...
  BFD_RELOC_TILEPRO_MMEND_X1,
  BFD_RELOC_TILEPRO_MMEND_X1,
  BFD_RELOC_TILEPRO_SHAMT_X0,
  BFD_RELOC_TILEPRO_SHAMT_X0,
  BFD_RELOC_TILEPRO_SHAMT_X1,
  BFD_RELOC_TILEPRO_SHAMT_X1,
  BFD_RELOC_TILEPRO_SHAMT_Y0,
  BFD_RELOC_TILEPRO_SHAMT_Y0,
  BFD_RELOC_TILEPRO_SHAMT_Y1,
  BFD_RELOC_TILEPRO_SHAMT_Y1,
 
  BFD_RELOC_TILEPRO_TLS_GD_CALL,
 
  BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD,
 
  BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD,
 
  BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD,
 
  BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD,
 
  BFD_RELOC_TILEPRO_TLS_IE_LOAD,
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD,
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD,
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD,
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD,
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO,
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO,
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO,
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO,
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI,
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI,
Line 4983... Line 5010...
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA,
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA,
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA,
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA,
  BFD_RELOC_TILEPRO_TLS_DTPMOD32,
  BFD_RELOC_TILEPRO_TLS_DTPMOD32,
  BFD_RELOC_TILEPRO_TLS_DTPOFF32,
  BFD_RELOC_TILEPRO_TLS_DTPOFF32,
  BFD_RELOC_TILEPRO_TLS_TPOFF32,
  BFD_RELOC_TILEPRO_TLS_TPOFF32,
 
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE,
 
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE,
 
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO,
 
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO,
 
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI,
 
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI,
 
  BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA,
 
  BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA,
 
 
/* Tilera TILE-Gx Relocations.  */
/* Tilera TILE-Gx Relocations.  */
  BFD_RELOC_TILEGX_HW0,
  BFD_RELOC_TILEGX_HW0,
  BFD_RELOC_TILEGX_HW1,
  BFD_RELOC_TILEGX_HW1,
  BFD_RELOC_TILEGX_HW2,
  BFD_RELOC_TILEGX_HW2,
Line 5042... Line 5077...
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL,
  BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL,
  BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL,
  BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL,
  BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT,
  BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE,
  BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE,
  BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE,
  BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE,
  BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD,
  BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE,
 
  BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE,
  BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE,
 
  BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE,
 
  BFD_RELOC_TILEGX_TLS_DTPMOD64,
  BFD_RELOC_TILEGX_TLS_DTPMOD64,
  BFD_RELOC_TILEGX_TLS_DTPOFF64,
  BFD_RELOC_TILEGX_TLS_DTPOFF64,
  BFD_RELOC_TILEGX_TLS_TPOFF64,
  BFD_RELOC_TILEGX_TLS_TPOFF64,
  BFD_RELOC_TILEGX_TLS_DTPMOD32,
  BFD_RELOC_TILEGX_TLS_DTPMOD32,
  BFD_RELOC_TILEGX_TLS_DTPOFF32,
  BFD_RELOC_TILEGX_TLS_DTPOFF32,
  BFD_RELOC_TILEGX_TLS_TPOFF32,
  BFD_RELOC_TILEGX_TLS_TPOFF32,
 
  BFD_RELOC_TILEGX_TLS_GD_CALL,
 
  BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD,
 
  BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD,
 
  BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD,
 
  BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD,
 
  BFD_RELOC_TILEGX_TLS_IE_LOAD,
 
  BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD,
 
  BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD,
 
  BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD,
 
  BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD,
 
 
/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement  */
/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement  */
  BFD_RELOC_EPIPHANY_SIMM8,
  BFD_RELOC_EPIPHANY_SIMM8,
 
 
/* Adapteva EPIPHANY - 24 bit signed pc-relative displacement  */
/* Adapteva EPIPHANY - 24 bit signed pc-relative displacement  */

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