| Line 87... |
Line 87... |
static int need_flag = 0;
|
static int need_flag = 0;
|
static int rl78_in_brackets = 0;
|
static int rl78_in_brackets = 0;
|
static int rl78_last_token = 0;
|
static int rl78_last_token = 0;
|
static char * rl78_init_start;
|
static char * rl78_init_start;
|
static char * rl78_last_exp_start = 0;
|
static char * rl78_last_exp_start = 0;
|
|
static int rl78_bit_insn = 0;
|
|
|
#define YYDEBUG 1
|
#define YYDEBUG 1
|
#define YYERROR_VERBOSE 1
|
#define YYERROR_VERBOSE 1
|
|
|
#define NOT_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFF1F")
|
#define NOT_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFF1F")
|
| Line 163... |
Line 164... |
%token DEC DECW DI DIVHU DIVWU
|
%token DEC DECW DI DIVHU DIVWU
|
%token EI
|
%token EI
|
%token HALT
|
%token HALT
|
%token INC INCW
|
%token INC INCW
|
%token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
|
%token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
|
%token NOP
|
%token NOP NOT1
|
%token ONEB ONEW OR OR1
|
%token ONEB ONEW OR OR1
|
%token POP PUSH
|
%token POP PUSH
|
%token RET RETI RETB ROL ROLC ROLWC ROR RORC
|
%token RET RETI RETB ROL ROLC ROLWC ROR RORC
|
%token SAR SARW SEL SET1 SHL SHLW SHR SHRW
|
%token SAR SARW SEL SET1 SHL SHLW SHR SHRW
|
%token SKC SKH SKNC SKNH SKNZ SKZ STOP SUB SUBC SUBW
|
%token SKC SKH SKNC SKNH SKNZ SKZ STOP SUB SUBC SUBW
|
| Line 216... |
Line 217... |
|
|
| addsub A ',' EXPR {SA($4)}
|
| addsub A ',' EXPR {SA($4)}
|
{ B1 (0x0b|$1); O1 ($4); }
|
{ B1 (0x0b|$1); O1 ($4); }
|
|
|
| addsub A ',' opt_es '!' EXPR
|
| addsub A ',' opt_es '!' EXPR
|
{ B1 (0x0f|$1); O2 ($6); }
|
{ B1 (0x0f|$1); O2 ($6); rl78_linkrelax_addr16 (); }
|
|
|
| addsub A ',' opt_es '[' HL ']'
|
| addsub A ',' opt_es '[' HL ']'
|
{ B1 (0x0d|$1); }
|
{ B1 (0x0d|$1); }
|
|
|
| addsub A ',' opt_es '[' HL '+' EXPR ']'
|
| addsub A ',' opt_es '[' HL '+' EXPR ']'
|
| Line 236... |
Line 237... |
|
|
| addsub opt_es '!' EXPR ',' '#' EXPR
|
| addsub opt_es '!' EXPR ',' '#' EXPR
|
{ if ($1 != 0x40)
|
{ if ($1 != 0x40)
|
{ rl78_error ("Only CMP takes these operands"); }
|
{ rl78_error ("Only CMP takes these operands"); }
|
else
|
else
|
{ B1 (0x00|$1); O2 ($4); O1 ($7); }
|
{ B1 (0x00|$1); O2 ($4); O1 ($7); rl78_linkrelax_addr16 (); }
|
}
|
}
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| addsubw AX ',' '#' EXPR
|
| addsubw AX ',' '#' EXPR
|
| Line 251... |
Line 252... |
|
|
| addsubw AX ',' EXPR {SA($4)}
|
| addsubw AX ',' EXPR {SA($4)}
|
{ B1 (0x06|$1); O1 ($4); }
|
{ B1 (0x06|$1); O1 ($4); }
|
|
|
| addsubw AX ',' opt_es '!' EXPR
|
| addsubw AX ',' opt_es '!' EXPR
|
{ B1 (0x02|$1); O2 ($6); }
|
{ B1 (0x02|$1); O2 ($6); rl78_linkrelax_addr16 (); }
|
|
|
| addsubw AX ',' opt_es '[' HL '+' EXPR ']'
|
| addsubw AX ',' opt_es '[' HL '+' EXPR ']'
|
{ B2 (0x61, 0x09|$1); O1 ($8); }
|
{ B2 (0x61, 0x09|$1); O1 ($8); }
|
|
|
| addsubw AX ',' opt_es '[' HL ']'
|
| addsubw AX ',' opt_es '[' HL ']'
|
| Line 334... |
Line 335... |
|
|
| BR '$' EXPR
|
| BR '$' EXPR
|
{ B1 (0xef); PC1 ($3); }
|
{ B1 (0xef); PC1 ($3); }
|
|
|
| BR '$' '!' EXPR
|
| BR '$' '!' EXPR
|
{ B1 (0xee); PC2 ($4); }
|
{ B1 (0xee); PC2 ($4); rl78_linkrelax_branch (); }
|
|
|
| BR '!' EXPR
|
| BR '!' EXPR
|
{ B1 (0xed); O2 ($3); }
|
{ B1 (0xed); O2 ($3); rl78_linkrelax_branch (); }
|
|
|
| BR '!' '!' EXPR
|
| BR '!' '!' EXPR
|
{ B1 (0xec); O3 ($4); }
|
{ B1 (0xec); O3 ($4); rl78_linkrelax_branch (); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| BRK
|
| BRK
|
{ B2 (0x61, 0xcc); }
|
{ B2 (0x61, 0xcc); }
|
| Line 362... |
Line 363... |
|
|
| CALL '!' EXPR
|
| CALL '!' EXPR
|
{ B1 (0xfd); O2 ($3); }
|
{ B1 (0xfd); O2 ($3); }
|
|
|
| CALL '!' '!' EXPR
|
| CALL '!' '!' EXPR
|
{ B1 (0xfc); O3 ($4); }
|
{ B1 (0xfc); O3 ($4); rl78_linkrelax_branch (); }
|
|
|
| CALLT '[' EXPR ']'
|
| CALLT '[' EXPR ']'
|
{ if ($3.X_op != O_constant)
|
{ if ($3.X_op != O_constant)
|
rl78_error ("CALLT requires a numeric address");
|
rl78_error ("CALLT requires a numeric address");
|
else
|
else
|
| Line 404... |
Line 405... |
|
|
| setclr1 A '.' EXPR
|
| setclr1 A '.' EXPR
|
{ B2 (0x71, 0x8a|$1); FE ($4, 9, 3); }
|
{ B2 (0x71, 0x8a|$1); FE ($4, 9, 3); }
|
|
|
| setclr1 opt_es '!' EXPR '.' EXPR
|
| setclr1 opt_es '!' EXPR '.' EXPR
|
{ B2 (0x71, 0x00+$1*0x08); FE ($6, 9, 3); O2 ($4); }
|
{ B2 (0x71, 0x00+$1*0x08); FE ($6, 9, 3); O2 ($4); rl78_linkrelax_addr16 (); }
|
|
|
| setclr1 opt_es '[' HL ']' '.' EXPR
|
| setclr1 opt_es '[' HL ']' '.' EXPR
|
{ B2 (0x71, 0x82|$1); FE ($7, 9, 3); }
|
{ B2 (0x71, 0x82|$1); FE ($7, 9, 3); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
| Line 424... |
Line 425... |
|
|
| oneclrb EXPR {SA($2)}
|
| oneclrb EXPR {SA($2)}
|
{ B1 (0xe4|$1); O1 ($2); }
|
{ B1 (0xe4|$1); O1 ($2); }
|
|
|
| oneclrb opt_es '!' EXPR
|
| oneclrb opt_es '!' EXPR
|
{ B1 (0xe5|$1); O2 ($4); }
|
{ B1 (0xe5|$1); O2 ($4); rl78_linkrelax_addr16 (); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| oneclrw AX
|
| oneclrw AX
|
{ B1 (0xe6|$1); }
|
{ B1 (0xe6|$1); }
|
| Line 451... |
Line 452... |
|
|
| CMP0 EXPR {SA($2)}
|
| CMP0 EXPR {SA($2)}
|
{ B1 (0xd4); O1 ($2); }
|
{ B1 (0xd4); O1 ($2); }
|
|
|
| CMP0 opt_es '!' EXPR
|
| CMP0 opt_es '!' EXPR
|
{ B1 (0xd5); O2 ($4); }
|
{ B1 (0xd5); O2 ($4); rl78_linkrelax_addr16 (); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| CMPS X ',' opt_es '[' HL '+' EXPR ']'
|
| CMPS X ',' opt_es '[' HL '+' EXPR ']'
|
{ B2 (0x61, 0xde); O1 ($8); }
|
{ B2 (0x61, 0xde); O1 ($8); }
|
| Line 466... |
Line 467... |
{ B1 (0x80|$1); F ($2, 5, 3); }
|
{ B1 (0x80|$1); F ($2, 5, 3); }
|
|
|
| incdec EXPR {SA($2)}
|
| incdec EXPR {SA($2)}
|
{ B1 (0xa4|$1); O1 ($2); }
|
{ B1 (0xa4|$1); O1 ($2); }
|
| incdec '!' EXPR
|
| incdec '!' EXPR
|
{ B1 (0xa0|$1); O2 ($3); }
|
{ B1 (0xa0|$1); O2 ($3); rl78_linkrelax_addr16 (); }
|
| incdec ES ':' '!' EXPR
|
| incdec ES ':' '!' EXPR
|
{ B2 (0x11, 0xa0|$1); O2 ($5); }
|
{ B2 (0x11, 0xa0|$1); O2 ($5); }
|
| incdec '[' HL '+' EXPR ']'
|
| incdec '[' HL '+' EXPR ']'
|
{ B2 (0x61, 0x59+$1); O1 ($5); }
|
{ B2 (0x61, 0x59+$1); O1 ($5); }
|
| incdec ES ':' '[' HL '+' EXPR ']'
|
| incdec ES ':' '[' HL '+' EXPR ']'
|
| Line 483... |
Line 484... |
|
|
| incdecw EXPR {SA($2)}
|
| incdecw EXPR {SA($2)}
|
{ B1 (0xa6|$1); O1 ($2); }
|
{ B1 (0xa6|$1); O1 ($2); }
|
|
|
| incdecw opt_es '!' EXPR
|
| incdecw opt_es '!' EXPR
|
{ B1 (0xa2|$1); O2 ($4); }
|
{ B1 (0xa2|$1); O2 ($4); rl78_linkrelax_addr16 (); }
|
|
|
| incdecw opt_es '[' HL '+' EXPR ']'
|
| incdecw opt_es '[' HL '+' EXPR ']'
|
{ B2 (0x61, 0x79+$1); O1 ($6); }
|
{ B2 (0x61, 0x79+$1); O1 ($6); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
| Line 551... |
Line 552... |
else
|
else
|
NOT_SFR_OR_SADDR;
|
NOT_SFR_OR_SADDR;
|
}
|
}
|
|
|
| MOV '!' EXPR ',' '#' EXPR
|
| MOV '!' EXPR ',' '#' EXPR
|
{ B1 (0xcf); O2 ($3); O1 ($6); }
|
{ B1 (0xcf); O2 ($3); O1 ($6); rl78_linkrelax_addr16 (); }
|
|
|
| MOV ES ':' '!' EXPR ',' '#' EXPR
|
| MOV ES ':' '!' EXPR ',' '#' EXPR
|
{ B2 (0x11, 0xcf); O2 ($5); O1 ($8); }
|
{ B2 (0x11, 0xcf); O2 ($5); O1 ($8); }
|
|
|
| MOV regb_na ',' A
|
| MOV regb_na ',' A
|
| Line 572... |
Line 573... |
else
|
else
|
NOT_SFR_OR_SADDR;
|
NOT_SFR_OR_SADDR;
|
}
|
}
|
|
|
| MOV A ',' opt_es '!' EXPR
|
| MOV A ',' opt_es '!' EXPR
|
{ B1 (0x8f); O2 ($6); }
|
{ B1 (0x8f); O2 ($6); rl78_linkrelax_addr16 (); }
|
|
|
| MOV '!' EXPR ',' A
|
| MOV '!' EXPR ',' A
|
{ B1 (0x9f); O2 ($3); }
|
{ B1 (0x9f); O2 ($3); rl78_linkrelax_addr16 (); }
|
|
|
| MOV ES ':' '!' EXPR ',' A
|
| MOV ES ':' '!' EXPR ',' A
|
{ B2 (0x11, 0x9f); O2 ($5); }
|
{ B2 (0x11, 0x9f); O2 ($5); }
|
|
|
| MOV regb_na ',' opt_es '!' EXPR
|
| MOV regb_na ',' opt_es '!' EXPR
|
{ B1 (0xc9|reg_xbc($2)); O2 ($6); }
|
{ B1 (0xc9|reg_xbc($2)); O2 ($6); rl78_linkrelax_addr16 (); }
|
|
|
| MOV A ',' opt_es EXPR {NOT_ES}
|
| MOV A ',' opt_es EXPR {NOT_ES}
|
{ if (expr_is_saddr ($5))
|
{ if (expr_is_saddr ($5))
|
{ B1 (0x8d); O1 ($5); }
|
{ B1 (0x8d); O1 ($5); }
|
else if (expr_is_sfr ($5))
|
else if (expr_is_sfr ($5))
|
| Line 710... |
Line 711... |
| MOV opt_es '[' SP ']' ',' A {NOT_ES}
|
| MOV opt_es '[' SP ']' ',' A {NOT_ES}
|
{ B2 (0x98, 0); }
|
{ B2 (0x98, 0); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| MOV1 CY ',' EXPR '.' EXPR
|
| mov1 CY ',' EXPR '.' EXPR
|
{ if (expr_is_saddr ($4))
|
{ if (expr_is_saddr ($4))
|
{ B2 (0x71, 0x04); FE ($6, 9, 3); O1 ($4); }
|
{ B2 (0x71, 0x04); FE ($6, 9, 3); O1 ($4); }
|
else if (expr_is_sfr ($4))
|
else if (expr_is_sfr ($4))
|
{ B2 (0x71, 0x0c); FE ($6, 9, 3); O1 ($4); }
|
{ B2 (0x71, 0x0c); FE ($6, 9, 3); O1 ($4); }
|
else
|
else
|
NOT_SFR_OR_SADDR;
|
NOT_SFR_OR_SADDR;
|
}
|
}
|
|
|
| MOV1 CY ',' A '.' EXPR
|
| mov1 CY ',' A '.' EXPR
|
{ B2 (0x71, 0x8c); FE ($6, 9, 3); }
|
{ B2 (0x71, 0x8c); FE ($6, 9, 3); }
|
|
|
| MOV1 CY ',' sfr '.' EXPR
|
| mov1 CY ',' sfr '.' EXPR
|
{ B3 (0x71, 0x0c, $4); FE ($6, 9, 3); }
|
{ B3 (0x71, 0x0c, $4); FE ($6, 9, 3); }
|
|
|
| MOV1 CY ',' opt_es '[' HL ']' '.' EXPR
|
| mov1 CY ',' opt_es '[' HL ']' '.' EXPR
|
{ B2 (0x71, 0x84); FE ($9, 9, 3); }
|
{ B2 (0x71, 0x84); FE ($9, 9, 3); }
|
|
|
| MOV1 EXPR '.' EXPR ',' CY
|
| mov1 EXPR '.' EXPR ',' CY
|
{ if (expr_is_saddr ($2))
|
{ if (expr_is_saddr ($2))
|
{ B2 (0x71, 0x01); FE ($4, 9, 3); O1 ($2); }
|
{ B2 (0x71, 0x01); FE ($4, 9, 3); O1 ($2); }
|
else if (expr_is_sfr ($2))
|
else if (expr_is_sfr ($2))
|
{ B2 (0x71, 0x09); FE ($4, 9, 3); O1 ($2); }
|
{ B2 (0x71, 0x09); FE ($4, 9, 3); O1 ($2); }
|
else
|
else
|
NOT_SFR_OR_SADDR;
|
NOT_SFR_OR_SADDR;
|
}
|
}
|
|
|
| MOV1 A '.' EXPR ',' CY
|
| mov1 A '.' EXPR ',' CY
|
{ B2 (0x71, 0x89); FE ($4, 9, 3); }
|
{ B2 (0x71, 0x89); FE ($4, 9, 3); }
|
|
|
| MOV1 sfr '.' EXPR ',' CY
|
| mov1 sfr '.' EXPR ',' CY
|
{ B3 (0x71, 0x09, $2); FE ($4, 9, 3); }
|
{ B3 (0x71, 0x09, $2); FE ($4, 9, 3); }
|
|
|
| MOV1 opt_es '[' HL ']' '.' EXPR ',' CY
|
| mov1 opt_es '[' HL ']' '.' EXPR ',' CY
|
{ B2 (0x71, 0x81); FE ($7, 9, 3); }
|
{ B2 (0x71, 0x81); FE ($7, 9, 3); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| MOVS opt_es '[' HL '+' EXPR ']' ',' X
|
| MOVS opt_es '[' HL '+' EXPR ']' ',' X
|
| Line 793... |
Line 794... |
|
|
| MOVW regw_na ',' AX
|
| MOVW regw_na ',' AX
|
{ B1 (0x10); F ($2, 5, 2); }
|
{ B1 (0x10); F ($2, 5, 2); }
|
|
|
| MOVW AX ',' opt_es '!' EXPR
|
| MOVW AX ',' opt_es '!' EXPR
|
{ B1 (0xaf); O2 ($6); WA($6); }
|
{ B1 (0xaf); O2 ($6); WA($6); rl78_linkrelax_addr16 (); }
|
|
|
| MOVW opt_es '!' EXPR ',' AX
|
| MOVW opt_es '!' EXPR ',' AX
|
{ B1 (0xbf); O2 ($4); WA($4); }
|
{ B1 (0xbf); O2 ($4); WA($4); rl78_linkrelax_addr16 (); }
|
|
|
| MOVW AX ',' opt_es '[' DE ']'
|
| MOVW AX ',' opt_es '[' DE ']'
|
{ B1 (0xa9); }
|
{ B1 (0xa9); }
|
|
|
| MOVW opt_es '[' DE ']' ',' AX
|
| MOVW opt_es '[' DE ']' ',' AX
|
| Line 862... |
Line 863... |
|
|
| MOVW regw_na ',' EXPR {SA($4)}
|
| MOVW regw_na ',' EXPR {SA($4)}
|
{ B1 (0xca); F ($2, 2, 2); O1 ($4); WA($4); }
|
{ B1 (0xca); F ($2, 2, 2); O1 ($4); WA($4); }
|
|
|
| MOVW regw_na ',' opt_es '!' EXPR
|
| MOVW regw_na ',' opt_es '!' EXPR
|
{ B1 (0xcb); F ($2, 2, 2); O2 ($6); WA($6); }
|
{ B1 (0xcb); F ($2, 2, 2); O2 ($6); WA($6); rl78_linkrelax_addr16 (); }
|
|
|
| MOVW SP ',' '#' EXPR
|
| MOVW SP ',' '#' EXPR
|
{ B2 (0xcb, 0xf8); O2 ($5); }
|
{ B2 (0xcb, 0xf8); O2 ($5); }
|
|
|
| MOVW SP ',' AX
|
| MOVW SP ',' AX
|
| Line 883... |
Line 884... |
| NOP
|
| NOP
|
{ B1 (0x00); }
|
{ B1 (0x00); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
|
| NOT1 CY
|
|
{ B2 (0x71, 0xc0); }
|
|
|
|
/* ---------------------------------------------------------------------- */
|
|
|
| POP regw
|
| POP regw
|
{ B1 (0xc0); F ($2, 5, 2); }
|
{ B1 (0xc0); F ($2, 5, 2); }
|
|
|
| POP PSW
|
| POP PSW
|
{ B2 (0x61, 0xcd); };
|
{ B2 (0x61, 0xcd); };
|
| Line 1006... |
Line 1012... |
}
|
}
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| SKC
|
| SKC
|
{ B2 (0x61, 0xc8); }
|
{ B2 (0x61, 0xc8); rl78_linkrelax_branch (); }
|
|
|
| SKH
|
| SKH
|
{ B2 (0x61, 0xe3); }
|
{ B2 (0x61, 0xe3); rl78_linkrelax_branch (); }
|
|
|
| SKNC
|
| SKNC
|
{ B2 (0x61, 0xd8); }
|
{ B2 (0x61, 0xd8); rl78_linkrelax_branch (); }
|
|
|
| SKNH
|
| SKNH
|
{ B2 (0x61, 0xf3); }
|
{ B2 (0x61, 0xf3); rl78_linkrelax_branch (); }
|
|
|
| SKNZ
|
| SKNZ
|
{ B2 (0x61, 0xf8); }
|
{ B2 (0x61, 0xf8); rl78_linkrelax_branch (); }
|
|
|
| SKZ
|
| SKZ
|
{ B2 (0x61, 0xe8); }
|
{ B2 (0x61, 0xe8); rl78_linkrelax_branch (); }
|
|
|
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
|
|
| STOP
|
| STOP
|
{ B2 (0x61, 0xfd); }
|
{ B2 (0x61, 0xfd); }
|
| Line 1038... |
Line 1044... |
else
|
else
|
{ B2 (0x61, 0x88); F ($4, 13, 3); }
|
{ B2 (0x61, 0x88); F ($4, 13, 3); }
|
}
|
}
|
|
|
| XCH A ',' opt_es '!' EXPR
|
| XCH A ',' opt_es '!' EXPR
|
{ B2 (0x61, 0xaa); O2 ($6); }
|
{ B2 (0x61, 0xaa); O2 ($6); rl78_linkrelax_addr16 (); }
|
|
|
| XCH A ',' opt_es '[' DE ']'
|
| XCH A ',' opt_es '[' DE ']'
|
{ B2 (0x61, 0xae); }
|
{ B2 (0x61, 0xae); }
|
|
|
| XCH A ',' opt_es '[' DE '+' EXPR ']'
|
| XCH A ',' opt_es '[' DE '+' EXPR ']'
|
| Line 1140... |
Line 1146... |
addsubw : ADDW { $$ = 0x00; }
|
addsubw : ADDW { $$ = 0x00; }
|
| SUBW { $$ = 0x20; }
|
| SUBW { $$ = 0x20; }
|
| CMPW { $$ = 0x40; }
|
| CMPW { $$ = 0x40; }
|
;
|
;
|
|
|
andor1 : AND1 { $$ = 0x05; }
|
andor1 : AND1 { $$ = 0x05; rl78_bit_insn = 1; }
|
| OR1 { $$ = 0x06; }
|
| OR1 { $$ = 0x06; rl78_bit_insn = 1;}
|
| XOR1 { $$ = 0x07; }
|
| XOR1 { $$ = 0x07; rl78_bit_insn = 1; }
|
;
|
;
|
|
|
bt_bf : BT { $$ = 0x02; }
|
bt_bf : BT { $$ = 0x02; rl78_bit_insn = 1;}
|
| BF { $$ = 0x04; }
|
| BF { $$ = 0x04; rl78_bit_insn = 1; }
|
| BTCLR { $$ = 0x00; }
|
| BTCLR { $$ = 0x00; rl78_bit_insn = 1; }
|
;
|
;
|
|
|
setclr1 : SET1 { $$ = 0; }
|
setclr1 : SET1 { $$ = 0; rl78_bit_insn = 1; }
|
| CLR1 { $$ = 1; }
|
| CLR1 { $$ = 1; rl78_bit_insn = 1; }
|
;
|
;
|
|
|
oneclrb : ONEB { $$ = 0x00; }
|
oneclrb : ONEB { $$ = 0x00; }
|
| CLRB { $$ = 0x10; }
|
| CLRB { $$ = 0x10; }
|
;
|
;
|
| Line 1170... |
Line 1176... |
|
|
incdecw : INCW { $$ = 0x00; }
|
incdecw : INCW { $$ = 0x00; }
|
| DECW { $$ = 0x10; }
|
| DECW { $$ = 0x10; }
|
;
|
;
|
|
|
|
mov1 : MOV1 { rl78_bit_insn = 1; }
|
|
;
|
|
|
%%
|
%%
|
/* ====================================================================== */
|
/* ====================================================================== */
|
|
|
static struct
|
static struct
|
{
|
{
|
| Line 1285... |
Line 1294... |
OPC(MOVW),
|
OPC(MOVW),
|
OPC(MULH),
|
OPC(MULH),
|
OPC(MULHU),
|
OPC(MULHU),
|
OPC(MULU),
|
OPC(MULU),
|
OPC(NOP),
|
OPC(NOP),
|
|
OPC(NOT1),
|
OPC(ONEB),
|
OPC(ONEB),
|
OPC(ONEW),
|
OPC(ONEW),
|
OPC(OR),
|
OPC(OR),
|
OPC(OR1),
|
OPC(OR1),
|
OPC(POP),
|
OPC(POP),
|
| Line 1334... |
Line 1344... |
rl78_lex_start = beginning;
|
rl78_lex_start = beginning;
|
rl78_lex_end = ending;
|
rl78_lex_end = ending;
|
rl78_in_brackets = 0;
|
rl78_in_brackets = 0;
|
rl78_last_token = 0;
|
rl78_last_token = 0;
|
|
|
|
rl78_bit_insn = 0;
|
|
|
setbuf (stdout, 0);
|
setbuf (stdout, 0);
|
}
|
}
|
|
|
|
/* Return a pointer to the '.' in a bit index expression (like
|
|
foo.5), or NULL if none is found. */
|
|
static char *
|
|
find_bit_index (char *tok)
|
|
{
|
|
char *last_dot = NULL;
|
|
char *last_digit = NULL;
|
|
while (*tok && *tok != ',')
|
|
{
|
|
if (*tok == '.')
|
|
{
|
|
last_dot = tok;
|
|
last_digit = NULL;
|
|
}
|
|
else if (*tok >= '0' && *tok <= '7'
|
|
&& last_dot != NULL
|
|
&& last_digit == NULL)
|
|
{
|
|
last_digit = tok;
|
|
}
|
|
else if (ISSPACE (*tok))
|
|
{
|
|
/* skip */
|
|
}
|
|
else
|
|
{
|
|
last_dot = NULL;
|
|
last_digit = NULL;
|
|
}
|
|
tok ++;
|
|
}
|
|
if (last_dot != NULL
|
|
&& last_digit != NULL)
|
|
return last_dot;
|
|
return NULL;
|
|
}
|
|
|
static int
|
static int
|
rl78_lex (void)
|
rl78_lex (void)
|
{
|
{
|
/*unsigned int ci;*/
|
/*unsigned int ci;*/
|
char * save_input_pointer;
|
char * save_input_pointer;
|
|
char * bit = NULL;
|
|
|
while (ISSPACE (*rl78_lex_start)
|
while (ISSPACE (*rl78_lex_start)
|
&& rl78_lex_start != rl78_lex_end)
|
&& rl78_lex_start != rl78_lex_end)
|
rl78_lex_start ++;
|
rl78_lex_start ++;
|
|
|
| Line 1398... |
Line 1448... |
|
|
/* '.' is funny - the syntax includes it for bitfields, but only for
|
/* '.' is funny - the syntax includes it for bitfields, but only for
|
bitfields. We check for it specially so we can allow labels
|
bitfields. We check for it specially so we can allow labels
|
with '.' in them. */
|
with '.' in them. */
|
|
|
if (*rl78_lex_start == '.'
|
if (rl78_bit_insn
|
&& ISDIGIT (rl78_lex_start[1])
|
&& *rl78_lex_start == '.'
|
&& (rl78_last_token == ']'
|
&& find_bit_index (rl78_lex_start) == rl78_lex_start)
|
|| rl78_last_token == A
|
|
|| rl78_last_token == PSW
|
|
|| rl78_last_token == EXPR))
|
|
{
|
{
|
rl78_last_token = *rl78_lex_start;
|
rl78_last_token = *rl78_lex_start;
|
return *rl78_lex_start ++;
|
return *rl78_lex_start ++;
|
}
|
}
|
|
|
| Line 1416... |
Line 1463... |
{
|
{
|
rl78_last_token = *rl78_lex_start;
|
rl78_last_token = *rl78_lex_start;
|
return *rl78_lex_start ++;
|
return *rl78_lex_start ++;
|
}
|
}
|
|
|
|
/* Again, '.' is funny. Look for '.' at the end of the line
|
|
or before a comma, which is a bitfield, not an expression. */
|
|
|
|
if (rl78_bit_insn)
|
|
{
|
|
bit = find_bit_index (rl78_lex_start);
|
|
if (bit)
|
|
*bit = 0;
|
|
else
|
|
bit = NULL;
|
|
}
|
|
|
save_input_pointer = input_line_pointer;
|
save_input_pointer = input_line_pointer;
|
input_line_pointer = rl78_lex_start;
|
input_line_pointer = rl78_lex_start;
|
rl78_lval.exp.X_md = 0;
|
rl78_lval.exp.X_md = 0;
|
expression (&rl78_lval.exp);
|
expression (&rl78_lval.exp);
|
|
|
|
if (bit)
|
|
*bit = '.';
|
|
|
rl78_lex_start = input_line_pointer;
|
rl78_lex_start = input_line_pointer;
|
input_line_pointer = save_input_pointer;
|
input_line_pointer = save_input_pointer;
|
rl78_last_token = EXPR;
|
rl78_last_token = EXPR;
|
return EXPR;
|
return EXPR;
|
}
|
}
|
|
|
int
|
int
|
rl78_error (char * str)
|
rl78_error (const char * str)
|
{
|
{
|
int len;
|
int len;
|
|
|
len = rl78_last_exp_start - rl78_init_start;
|
len = rl78_last_exp_start - rl78_init_start;
|
|
|
