| Line 7796... |
Line 7796... |
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static void
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static void
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do_ldrd (void)
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do_ldrd (void)
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{
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{
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constraint (inst.operands[0].reg % 2 != 0,
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constraint (inst.operands[0].reg % 2 != 0,
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_("first destination register must be even"));
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_("first transfer register must be even"));
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constraint (inst.operands[1].present
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constraint (inst.operands[1].present
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&& inst.operands[1].reg != inst.operands[0].reg + 1,
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&& inst.operands[1].reg != inst.operands[0].reg + 1,
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_("can only load two consecutive registers"));
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_("can only transfer two consecutive registers"));
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constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
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constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
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constraint (!inst.operands[2].isreg, _("'[' expected"));
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constraint (!inst.operands[2].isreg, _("'[' expected"));
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if (!inst.operands[1].present)
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if (!inst.operands[1].present)
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inst.operands[1].reg = inst.operands[0].reg + 1;
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inst.operands[1].reg = inst.operands[0].reg + 1;
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if (inst.instruction & LOAD_BIT)
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{
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/* encode_arm_addr_mode_3 will diagnose overlap between the base
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/* encode_arm_addr_mode_3 will diagnose overlap between the base
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register and the first register written; we have to diagnose
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register and the first register written; we have to diagnose
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overlap between the base and the second register written here. */
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overlap between the base and the second register written here. */
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if (inst.operands[2].reg == inst.operands[1].reg
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if (inst.operands[2].reg == inst.operands[1].reg
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&& (inst.operands[2].writeback || inst.operands[2].postind))
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&& (inst.operands[2].writeback || inst.operands[2].postind))
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as_warn (_("base register written back, and overlaps "
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as_warn (_("base register written back, and overlaps "
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"second destination register"));
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"second transfer register"));
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if (!(inst.instruction & V4_STR_BIT))
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{
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/* For an index-register load, the index register must not overlap the
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/* For an index-register load, the index register must not overlap the
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destination (even if not write-back). */
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destination (even if not write-back). */
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else if (inst.operands[2].immisreg
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if (inst.operands[2].immisreg
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&& ((unsigned) inst.operands[2].imm == inst.operands[0].reg
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&& ((unsigned) inst.operands[2].imm == inst.operands[0].reg
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|| (unsigned) inst.operands[2].imm == inst.operands[1].reg))
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|| (unsigned) inst.operands[2].imm == inst.operands[1].reg))
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as_warn (_("index register overlaps destination register"));
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as_warn (_("index register overlaps transfer register"));
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}
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}
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= inst.operands[0].reg << 12;
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encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
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encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
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}
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}
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static void
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static void
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| Line 8342... |
Line 8341... |
inst.instruction |= Rm;
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inst.instruction |= Rm;
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if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
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if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
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{
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{
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inst.instruction |= inst.operands[2].reg << 8;
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inst.instruction |= inst.operands[2].reg << 8;
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inst.instruction |= SHIFT_BY_REG;
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inst.instruction |= SHIFT_BY_REG;
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/* PR 12854: Error on extraneous shifts. */
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constraint (inst.operands[2].shifted,
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_("extraneous shift as part of operand to shift insn"));
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}
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}
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else
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else
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inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
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inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
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}
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}
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| Line 11534... |
Line 11536... |
reject_bad_reg (inst.operands[2].reg);
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reject_bad_reg (inst.operands[2].reg);
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inst.instruction = THUMB_OP32 (inst.instruction);
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inst.instruction = THUMB_OP32 (inst.instruction);
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inst.instruction |= inst.operands[0].reg << 8;
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inst.instruction |= inst.operands[0].reg << 8;
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inst.instruction |= inst.operands[1].reg << 16;
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inst.instruction |= inst.operands[1].reg << 16;
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inst.instruction |= inst.operands[2].reg;
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inst.instruction |= inst.operands[2].reg;
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/* PR 12854: Error on extraneous shifts. */
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constraint (inst.operands[2].shifted,
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_("extraneous shift as part of operand to shift insn"));
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}
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}
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else
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else
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{
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{
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inst.operands[1].shifted = 1;
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inst.operands[1].shifted = 1;
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inst.operands[1].shift_kind = shift_kind;
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inst.operands[1].shift_kind = shift_kind;
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| Line 11562... |
Line 11568... |
default: abort ();
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default: abort ();
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}
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}
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inst.instruction |= inst.operands[0].reg;
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inst.instruction |= inst.operands[0].reg;
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inst.instruction |= inst.operands[2].reg << 3;
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inst.instruction |= inst.operands[2].reg << 3;
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/* PR 12854: Error on extraneous shifts. */
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constraint (inst.operands[2].shifted,
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_("extraneous shift as part of operand to shift insn"));
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}
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}
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else
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else
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{
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{
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switch (shift_kind)
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switch (shift_kind)
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{
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{
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| Line 11601... |
Line 11611... |
default: abort ();
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default: abort ();
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}
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}
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inst.instruction |= inst.operands[0].reg;
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inst.instruction |= inst.operands[0].reg;
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inst.instruction |= inst.operands[2].reg << 3;
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inst.instruction |= inst.operands[2].reg << 3;
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/* PR 12854: Error on extraneous shifts. */
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constraint (inst.operands[2].shifted,
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_("extraneous shift as part of operand to shift insn"));
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}
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}
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else
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else
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{
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{
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switch (inst.instruction)
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switch (inst.instruction)
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{
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{
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