| Line 30... |
Line 30... |
#include <stdarg.h>
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#include <stdarg.h>
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#define NO_RELOC 0
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#define NO_RELOC 0
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#include "safe-ctype.h"
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#include "safe-ctype.h"
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#include "subsegs.h"
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#include "subsegs.h"
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#include "obstack.h"
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#include "obstack.h"
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#include "libiberty.h"
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#include "opcode/arm.h"
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#include "opcode/arm.h"
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#ifdef OBJ_ELF
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#ifdef OBJ_ELF
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#include "elf/arm.h"
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#include "elf/arm.h"
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#include "dw2gencfi.h"
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#include "dw2gencfi.h"
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| Line 2052... |
Line 2052... |
/* Parse an explicit relocation suffix on an expression. This is
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/* Parse an explicit relocation suffix on an expression. This is
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either nothing, or a word in parentheses. Note that if !OBJ_ELF,
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either nothing, or a word in parentheses. Note that if !OBJ_ELF,
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arm_reloc_hsh contains no entries, so this function can only
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arm_reloc_hsh contains no entries, so this function can only
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succeed if there is no () after the word. Returns -1 on error,
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succeed if there is no () after the word. Returns -1 on error,
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BFD_RELOC_UNUSED if there wasn't any suffix. */
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BFD_RELOC_UNUSED if there wasn't any suffix. */
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static int
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static int
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parse_reloc (char **str)
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parse_reloc (char **str)
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{
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{
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struct reloc_entry *r;
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struct reloc_entry *r;
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char *p, *q;
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char *p, *q;
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| Line 4882... |
Line 4883... |
{
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{
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inst.error = _("invalid constant");
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inst.error = _("invalid constant");
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return FAIL;
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return FAIL;
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}
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}
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/* Convert to decoded value. md_apply_fix will put it back. */
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/* Encode as specified. */
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inst.reloc.exp.X_add_number
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inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
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= (((inst.reloc.exp.X_add_number << (32 - value))
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return SUCCESS;
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| (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
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}
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}
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inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
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inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
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inst.reloc.pc_rel = 0;
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inst.reloc.pc_rel = 0;
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return SUCCESS;
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return SUCCESS;
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| Line 7016... |
Line 7016... |
{
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{
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inst.instruction |= inst.operands[i].reg;
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inst.instruction |= inst.operands[i].reg;
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encode_arm_shift (i);
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encode_arm_shift (i);
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}
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}
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else
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else
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{
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inst.instruction |= INST_IMMEDIATE;
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inst.instruction |= INST_IMMEDIATE;
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if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
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inst.instruction |= inst.operands[i].imm;
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}
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}
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}
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/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
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/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
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static void
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static void
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encode_arm_addr_mode_common (int i, bfd_boolean is_t)
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encode_arm_addr_mode_common (int i, bfd_boolean is_t)
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| Line 7913... |
Line 7917... |
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= inst.operands[2].reg << 16;
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inst.instruction |= inst.operands[2].reg << 16;
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}
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}
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/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
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which is not a multiple of four is UNPREDICTABLE. */
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static void
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check_ldr_r15_aligned (void)
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{
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constraint (!(inst.operands[1].immisreg)
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&& (inst.operands[0].reg == REG_PC
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&& inst.operands[1].reg == REG_PC
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&& (inst.reloc.exp.X_add_number & 0x3)),
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_("ldr to register 15 must be 4-byte alligned"));
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}
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static void
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static void
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do_ldst (void)
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do_ldst (void)
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{
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{
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= inst.operands[0].reg << 12;
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if (!inst.operands[1].isreg)
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if (!inst.operands[1].isreg)
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if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
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if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
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return;
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return;
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encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
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encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
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check_ldr_r15_aligned ();
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}
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}
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static void
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static void
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do_ldstt (void)
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do_ldstt (void)
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{
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{
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| Line 10531... |
Line 10548... |
"if executed on M-profile cores "
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"if executed on M-profile cores "
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"with interrupts enabled."));
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"with interrupts enabled."));
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}
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}
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/* Do some validations regarding addressing modes. */
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/* Do some validations regarding addressing modes. */
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if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
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if (inst.operands[1].immisreg)
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&& opcode != T_MNEM_str)
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reject_bad_reg (inst.operands[1].imm);
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reject_bad_reg (inst.operands[1].imm);
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constraint (inst.operands[1].writeback == 1
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&& inst.operands[0].reg == inst.operands[1].reg,
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BAD_OVERLAP);
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inst.instruction = THUMB_OP32 (opcode);
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inst.instruction = THUMB_OP32 (opcode);
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= inst.operands[0].reg << 12;
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encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
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encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
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check_ldr_r15_aligned ();
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return;
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return;
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}
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}
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constraint (inst.operands[0].reg > 7, BAD_HIREG);
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constraint (inst.operands[0].reg > 7, BAD_HIREG);
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| Line 22398... |
Line 22419... |
i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
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i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
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i++)
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i++)
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hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
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hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
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(void *) (barrier_opt_names + i));
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(void *) (barrier_opt_names + i));
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#ifdef OBJ_ELF
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#ifdef OBJ_ELF
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for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
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for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
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hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
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{
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struct reloc_entry * entry = reloc_names + i;
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if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
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/* This makes encode_branch() use the EABI versions of this relocation. */
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entry->reloc = BFD_RELOC_UNUSED;
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hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
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}
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#endif
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#endif
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set_constant_flonums ();
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set_constant_flonums ();
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/* Set the cpu variant based on the command-line options. We prefer
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/* Set the cpu variant based on the command-line options. We prefer
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| Line 22931... |
Line 22960... |
{"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
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{"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
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{"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
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{"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
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{"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
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{"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
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{"cortex-a5", ARM_ARCH_V7A_MP_SEC,
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{"cortex-a5", ARM_ARCH_V7A_MP_SEC,
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FPU_NONE, "Cortex-A5"},
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FPU_NONE, "Cortex-A5"},
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{"cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
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FPU_ARCH_NEON_VFP_V4,
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"Cortex-A7"},
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{"cortex-a8", ARM_ARCH_V7A_SEC,
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{"cortex-a8", ARM_ARCH_V7A_SEC,
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ARM_FEATURE (0, FPU_VFP_V3
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ARM_FEATURE (0, FPU_VFP_V3
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| FPU_NEON_EXT_V1),
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| FPU_NEON_EXT_V1),
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"Cortex-A8"},
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"Cortex-A8"},
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{"cortex-a9", ARM_ARCH_V7A_MP_SEC,
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{"cortex-a9", ARM_ARCH_V7A_MP_SEC,
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