OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [gas/] [doc/] [c-i386.texi] - Diff between revs 148 and 160

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 148 Rev 160
Line 109... Line 109...
@code{nocona},
@code{nocona},
@code{core},
@code{core},
@code{core2},
@code{core2},
@code{corei7},
@code{corei7},
@code{l1om},
@code{l1om},
 
@code{k1om},
@code{k6},
@code{k6},
@code{k6_2},
@code{k6_2},
@code{athlon},
@code{athlon},
@code{opteron},
@code{opteron},
@code{k8},
@code{k8},
Line 208... Line 209...
 
 
@cindex @samp{-mavxscalar=} option, i386
@cindex @samp{-mavxscalar=} option, i386
@cindex @samp{-mavxscalar=} option, x86-64
@cindex @samp{-mavxscalar=} option, x86-64
@item -mavxscalar=@var{128}
@item -mavxscalar=@var{128}
@itemx -mavxscalar=@var{256}
@itemx -mavxscalar=@var{256}
This options control how the assembler should encode scalar AVX
These options control how the assembler should encode scalar AVX
instructions.  @option{-mavxscalar=@var{128}} will encode scalar
instructions.  @option{-mavxscalar=@var{128}} will encode scalar
AVX instructions with 128bit vector length, which is the default.
AVX instructions with 128bit vector length, which is the default.
@option{-mavxscalar=@var{256}} will encode scalar AVX instructions
@option{-mavxscalar=@var{256}} will encode scalar AVX instructions
with 256bit vector length.
with 256bit vector length.
 
 
Line 1001... Line 1002...
@multitable @columnfractions .20 .20 .20 .20
@multitable @columnfractions .20 .20 .20 .20
@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
@item @samp{corei7} @tab @samp{l1om}
@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2}
@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2}
@item @samp{generic32} @tab @samp{generic64}
@item @samp{generic32} @tab @samp{generic64}
@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.