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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
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"a" 26-bit target address (MICROMIPSOP_*_TARGET)
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"a" 26-bit target address (MICROMIPSOP_*_TARGET)
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"b" 5-bit base register (MICROMIPSOP_*_RS)
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"b" 5-bit base register (MICROMIPSOP_*_RS)
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"c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
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"c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
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"d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
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"d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
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"h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
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"h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
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"i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
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"i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
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"j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
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"j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
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"k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
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"k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
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"n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
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"n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
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"o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
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"o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
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"p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
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"p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
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