| Line 711... |
Line 711... |
is non-zero. */
|
is non-zero. */
|
static const unsigned int mips_isa_table[] =
|
static const unsigned int mips_isa_table[] =
|
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
|
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
|
|
|
/* Masks used for Chip specific instructions. */
|
/* Masks used for Chip specific instructions. */
|
#define INSN_CHIP_MASK 0xc3ff0c20
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#define INSN_CHIP_MASK 0xc3ff0f20
|
|
|
/* Cavium Networks Octeon instructions. */
|
/* Cavium Networks Octeon instructions. */
|
#define INSN_OCTEON 0x00000800
|
#define INSN_OCTEON 0x00000800
|
|
#define INSN_OCTEONP 0x00000200
|
|
#define INSN_OCTEON2 0x00000100
|
|
|
/* Masks used for MIPS-defined ASEs. */
|
/* Masks used for MIPS-defined ASEs. */
|
#define INSN_ASE_MASK 0x3c00f010
|
#define INSN_ASE_MASK 0x3c00f010
|
|
|
/* DSP ASE */
|
/* DSP ASE */
|
| Line 821... |
Line 823... |
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
#define CPU_LOONGSON_2E 3001
|
#define CPU_LOONGSON_2E 3001
|
#define CPU_LOONGSON_2F 3002
|
#define CPU_LOONGSON_2F 3002
|
#define CPU_LOONGSON_3A 3003
|
#define CPU_LOONGSON_3A 3003
|
#define CPU_OCTEON 6501
|
#define CPU_OCTEON 6501
|
|
#define CPU_OCTEONP 6601
|
|
#define CPU_OCTEON2 6502
|
#define CPU_XLR 887682 /* decimal 'XLR' */
|
#define CPU_XLR 887682 /* decimal 'XLR' */
|
|
|
/* Test for membership in an ISA including chip specific ISAs. INSN
|
/* Test for membership in an ISA including chip specific ISAs. INSN
|
is pointer to an element of the opcode table; ISA is the specified
|
is pointer to an element of the opcode table; ISA is the specified
|
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
| Line 857... |
Line 861... |
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
|
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
|
|| (cpu == CPU_LOONGSON_3A \
|
|| (cpu == CPU_LOONGSON_3A \
|
&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|
&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|
|| (cpu == CPU_OCTEON \
|
|| (cpu == CPU_OCTEON \
|
&& ((insn)->membership & INSN_OCTEON) != 0) \
|
&& ((insn)->membership & INSN_OCTEON) != 0) \
|
|
|| (cpu == CPU_OCTEONP \
|
|
&& ((insn)->membership & INSN_OCTEONP) != 0) \
|
|
|| (cpu == CPU_OCTEON2 \
|
|
&& ((insn)->membership & INSN_OCTEON2) != 0) \
|
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|
|| 0) /* Please keep this term for easier source merging. */
|
|| 0) /* Please keep this term for easier source merging. */
|
|
|
/* This is a list of macro expanded instructions.
|
/* This is a list of macro expanded instructions.
|
|
|
| Line 1063... |
Line 1071... |
M_ROR_I,
|
M_ROR_I,
|
M_S_DA,
|
M_S_DA,
|
M_S_DOB,
|
M_S_DOB,
|
M_S_DAB,
|
M_S_DAB,
|
M_S_S,
|
M_S_S,
|
|
M_SAA_AB,
|
|
M_SAA_OB,
|
|
M_SAAD_AB,
|
|
M_SAAD_OB,
|
M_SC_AB,
|
M_SC_AB,
|
M_SC_OB,
|
M_SC_OB,
|
M_SCD_AB,
|
M_SCD_AB,
|
M_SCD_OB,
|
M_SCD_OB,
|
M_SD_A,
|
M_SD_A,
|
