| Line 129... |
Line 129... |
v frs1 floating point register (double/even).
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v frs1 floating point register (double/even).
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V frs1 floating point register (quad/multiple of 4).
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V frs1 floating point register (quad/multiple of 4).
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f frs2 floating point register.
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f frs2 floating point register.
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B frs2 floating point register (double/even).
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B frs2 floating point register (double/even).
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R frs2 floating point register (quad/multiple of 4).
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R frs2 floating point register (quad/multiple of 4).
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4 frs3 floating point register.
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5 frs3 floating point register (doube/even).
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g frsd floating point register.
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g frsd floating point register.
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H frsd floating point register (double/even).
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H frsd floating point register (double/even).
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J frsd floating point register (quad/multiple of 4).
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J frsd floating point register (quad/multiple of 4).
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b crs1 coprocessor register
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b crs1 coprocessor register
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c crs2 coprocessor register
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c crs2 coprocessor register
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| Line 185... |
Line 187... |
* Prefetch function constant. (v9)
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* Prefetch function constant. (v9)
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x OPF field (v9 impdep).
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x OPF field (v9 impdep).
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0 32/64 bit immediate for set or setx (v9) insns
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0 32/64 bit immediate for set or setx (v9) insns
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_ Ancillary state register in rd (v9a)
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_ Ancillary state register in rd (v9a)
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/ Ancillary state register in rs1 (v9a)
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/ Ancillary state register in rs1 (v9a)
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( entire floating point state register (%efsr). */
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The following chars are unused: (note: ,[] are used as punctuation)
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[45]. */
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#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
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#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
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#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
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#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
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#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
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#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
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#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
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#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
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#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
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#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
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#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
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#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
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#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
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#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
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#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
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#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
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#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
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#define F1(x) (OP (x))
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#define F1(x) (OP (x))
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| Line 205... |
Line 206... |
#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
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#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
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#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
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#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
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#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
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#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
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#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
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#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
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#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
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#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
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#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */
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#define ASI_RS2(x) (SIMM13 (x))
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#define ASI_RS2(x) (SIMM13 (x))
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#define MEMBAR(x) ((x) & 0x7f)
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#define MEMBAR(x) ((x) & 0x7f)
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#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
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#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
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#define ANNUL (1 << 29)
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#define ANNUL (1 << 29)
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