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/* Definitions for opcode table for the sparc.
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/* Definitions for opcode table for the sparc.
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
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2003, 2005, 2010 Free Software Foundation, Inc.
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2003, 2005, 2010, 2011 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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GAS/GDB is free software; you can redistribute it and/or modify
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const char *name;
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const char *name;
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unsigned long match; /* Bits that must be set. */
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unsigned long match; /* Bits that must be set. */
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unsigned long lose; /* Bits that must not be set. */
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unsigned long lose; /* Bits that must not be set. */
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const char *args;
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const char *args;
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/* This was called "delayed" in versions before the flags. */
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/* This was called "delayed" in versions before the flags. */
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char flags;
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unsigned int flags;
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short architecture; /* Bitmask of sparc_opcode_arch_val's. */
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short architecture; /* Bitmask of sparc_opcode_arch_val's. */
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} sparc_opcode;
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} sparc_opcode;
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#define F_DELAYED 1 /* Delayed branch. */
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#define F_ALIAS 2 /* Alias for a "real" instruction. */
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#define F_UNBR 4 /* Unconditional branch. */
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#define F_CONDBR 8 /* Conditional branch. */
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#define F_JSR 16 /* Subroutine call. */
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#define F_FLOAT 32 /* Floating point instruction (not a branch). */
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#define F_FBR 64 /* Floating point branch. */
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/* FIXME: Add F_ANACHRONISTIC flag for v9. */
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/* FIXME: Add F_ANACHRONISTIC flag for v9. */
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#define F_DELAYED 0x00000001 /* Delayed branch. */
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#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */
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#define F_UNBR 0x00000004 /* Unconditional branch. */
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#define F_CONDBR 0x00000008 /* Conditional branch. */
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#define F_JSR 0x00000010 /* Subroutine call. */
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#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
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#define F_FBR 0x00000040 /* Floating point branch. */
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#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */
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#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
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#define F_FSMULD 0x00000400 /* 'fsmuld' insn */
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#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */
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#define F_POPC 0x00001000 /* 'popc' insn */
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#define F_VIS 0x00002000 /* VIS insns */
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#define F_VIS2 0x00004000 /* VIS2 insns */
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#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */
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#define F_FMAF 0x00010000 /* fused multiply-add */
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#define F_VIS3 0x00020000 /* VIS3 insns */
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#define F_HPC 0x00040000 /* HPC insns */
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#define F_RANDOM 0x00080000 /* 'random' insn */
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#define F_TRANS 0x00100000 /* transaction insns */
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#define F_FJFMAU 0x00200000 /* unfused multiply-add */
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#define F_IMA 0x00400000 /* integer multiply-add */
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#define F_ASI_CACHE_SPARING \
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0x00800000 /* cache sparing ASIs */
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#define F_HWCAP_MASK 0x00ffff00
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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macro), which is 64 bits. It is handled as a special case.
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macro), which is 64 bits. It is handled as a special case.
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The match component is a mask saying which bits must match a particular
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The match component is a mask saying which bits must match a particular
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