| Line 90... |
Line 90... |
CpuSSE4_1,
|
CpuSSE4_1,
|
/* SSE4.2 support required */
|
/* SSE4.2 support required */
|
CpuSSE4_2,
|
CpuSSE4_2,
|
/* AVX support required */
|
/* AVX support required */
|
CpuAVX,
|
CpuAVX,
|
|
/* AVX2 support required */
|
|
CpuAVX2,
|
/* Intel L1OM support required */
|
/* Intel L1OM support required */
|
CpuL1OM,
|
CpuL1OM,
|
/* Xsave/xrstor New Instructions support required */
|
/* Xsave/xrstor New Instructions support required */
|
CpuXsave,
|
CpuXsave,
|
/* Xsaveopt New Instructions support required */
|
/* Xsaveopt New Instructions support required */
|
| Line 124... |
Line 126... |
CpuFSGSBase,
|
CpuFSGSBase,
|
/* RDRND Instructions required */
|
/* RDRND Instructions required */
|
CpuRdRnd,
|
CpuRdRnd,
|
/* F16C Instructions required */
|
/* F16C Instructions required */
|
CpuF16C,
|
CpuF16C,
|
|
/* Intel BMI2 support required */
|
|
CpuBMI2,
|
|
/* LZCNT support required */
|
|
CpuLZCNT,
|
|
/* INVPCID Instructions required */
|
|
CpuINVPCID,
|
/* 64bit support available, used by -march= in assembler. */
|
/* 64bit support available, used by -march= in assembler. */
|
CpuLM,
|
CpuLM,
|
/* 64bit support required */
|
/* 64bit support required */
|
Cpu64,
|
Cpu64,
|
/* Not supported in the 64bit mode */
|
/* Not supported in the 64bit mode */
|
| Line 179... |
Line 187... |
unsigned int cpusse4a:1;
|
unsigned int cpusse4a:1;
|
unsigned int cpuabm:1;
|
unsigned int cpuabm:1;
|
unsigned int cpusse4_1:1;
|
unsigned int cpusse4_1:1;
|
unsigned int cpusse4_2:1;
|
unsigned int cpusse4_2:1;
|
unsigned int cpuavx:1;
|
unsigned int cpuavx:1;
|
|
unsigned int cpuavx2:1;
|
unsigned int cpul1om:1;
|
unsigned int cpul1om:1;
|
unsigned int cpuxsave:1;
|
unsigned int cpuxsave:1;
|
unsigned int cpuxsaveopt:1;
|
unsigned int cpuxsaveopt:1;
|
unsigned int cpuaes:1;
|
unsigned int cpuaes:1;
|
unsigned int cpupclmul:1;
|
unsigned int cpupclmul:1;
|
| Line 196... |
Line 205... |
unsigned int cpuept:1;
|
unsigned int cpuept:1;
|
unsigned int cpurdtscp:1;
|
unsigned int cpurdtscp:1;
|
unsigned int cpufsgsbase:1;
|
unsigned int cpufsgsbase:1;
|
unsigned int cpurdrnd:1;
|
unsigned int cpurdrnd:1;
|
unsigned int cpuf16c:1;
|
unsigned int cpuf16c:1;
|
|
unsigned int cpubmi2:1;
|
|
unsigned int cpulzcnt:1;
|
|
unsigned int cpuinvpcid:1;
|
unsigned int cpulm:1;
|
unsigned int cpulm:1;
|
unsigned int cpu64:1;
|
unsigned int cpu64:1;
|
unsigned int cpuno64:1;
|
unsigned int cpuno64:1;
|
#ifdef CpuUnused
|
#ifdef CpuUnused
|
unsigned int unused:(CpuNumOfBits - CpuUnused);
|
unsigned int unused:(CpuNumOfBits - CpuUnused);
|
| Line 305... |
Line 317... |
1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
|
1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
|
the content of source registers will be preserved.
|
the content of source registers will be preserved.
|
VEX.DDS. The second register operand is encoded in VEX.vvvv
|
VEX.DDS. The second register operand is encoded in VEX.vvvv
|
where the content of first source register will be overwritten
|
where the content of first source register will be overwritten
|
by the result.
|
by the result.
|
For assembler, there are no difference between VEX.NDS and
|
VEX.NDD2. The second destination register operand is encoded in
|
VEX.DDS.
|
VEX.vvvv for instructions with 2 destination register operands.
|
2. VEX.NDD. Register destination is encoded in VEX.vvvv.
|
For assembler, there are no difference between VEX.NDS, VEX.DDS
|
|
and VEX.NDD2.
|
|
2. VEX.NDD. Register destination is encoded in VEX.vvvv for
|
|
instructions with 1 destination register operand.
|
3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
|
3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
|
of the operands can access a memory location.
|
of the operands can access a memory location.
|
*/
|
*/
|
#define VEXXDS 1
|
#define VEXXDS 1
|
#define VEXNDD 2
|
#define VEXNDD 2
|
| Line 348... |
Line 363... |
#define XOP2SOURCES 1
|
#define XOP2SOURCES 1
|
#define VEX3SOURCES 2
|
#define VEX3SOURCES 2
|
VexSources,
|
VexSources,
|
/* instruction has VEX 8 bit imm */
|
/* instruction has VEX 8 bit imm */
|
VexImmExt,
|
VexImmExt,
|
|
/* Instruction with vector SIB byte:
|
|
1: 128bit vector register.
|
|
2: 256bit vector register.
|
|
*/
|
|
#define VecSIB128 1
|
|
#define VecSIB256 2
|
|
VecSIB,
|
/* SSE to AVX support required */
|
/* SSE to AVX support required */
|
SSE2AVX,
|
SSE2AVX,
|
/* No AVX equivalent */
|
/* No AVX equivalent */
|
NoAVX,
|
NoAVX,
|
/* Compatible with old (<= 2.8.1) versions of gcc */
|
/* Compatible with old (<= 2.8.1) versions of gcc */
|
| Line 410... |
Line 432... |
unsigned int vexvvvv:2;
|
unsigned int vexvvvv:2;
|
unsigned int vexw:2;
|
unsigned int vexw:2;
|
unsigned int vexopcode:3;
|
unsigned int vexopcode:3;
|
unsigned int vexsources:2;
|
unsigned int vexsources:2;
|
unsigned int veximmext:1;
|
unsigned int veximmext:1;
|
|
unsigned int vecsib:2;
|
unsigned int sse2avx:1;
|
unsigned int sse2avx:1;
|
unsigned int noavx:1;
|
unsigned int noavx:1;
|
unsigned int oldgcc:1;
|
unsigned int oldgcc:1;
|
unsigned int attmnemonic:1;
|
unsigned int attmnemonic:1;
|
unsigned int attsyntax:1;
|
unsigned int attsyntax:1;
|
