| Line 56... |
Line 56... |
#define WR_HI INSN_WRITE_HI
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#define WR_HI INSN_WRITE_HI
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#define WR_LO INSN_WRITE_LO
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#define WR_LO INSN_WRITE_LO
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#define RD_HI INSN_READ_HI
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#define RD_HI INSN_READ_HI
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#define RD_LO INSN_READ_LO
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#define RD_LO INSN_READ_LO
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#define TRAP INSN_TRAP
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#define NODS INSN_NO_DELAY_SLOT
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#define TRAP INSN_NO_DELAY_SLOT
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#define I1 INSN_ISA1
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#define I1 INSN_ISA1
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#define I3 INSN_ISA3
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#define I3 INSN_ISA3
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#define I32 INSN_ISA32
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#define I32 INSN_ISA32
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#define I64 INSN_ISA64
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#define I64 INSN_ISA64
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| Line 169... |
Line 170... |
{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, I1 },
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{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, I1 },
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{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
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{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
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{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
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{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
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{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
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{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
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{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
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{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
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/* MIPS16e compact branches. We keep them near the ordinary branches
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so that we easily find them when converting a normal branch to a
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compact one. */
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{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
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{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32 },
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{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32 },
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{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 },
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{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 },
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{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 },
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{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 },
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{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
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{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
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{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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| Line 225... |
Line 233... |
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1 },
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{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1 },
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{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1 },
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{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1 },
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{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 },
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{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 },
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{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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/* MIPS16e additions */
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/* MIPS16e additions */
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{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 },
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{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 },
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{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32 },
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{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|TRAP, 0, I32 },
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{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|TRAP, 0, I32 },
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{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, I32 },
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{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, I32 },
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{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 },
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{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 },
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{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 },
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{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 },
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{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 },
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{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 },
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{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64 },
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{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64 },
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{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32 },
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{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32 },
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