| Line 106... |
Line 106... |
/* These are ordered according to there register number in
|
/* These are ordered according to there register number in
|
rd and wr insns (-16). */
|
rd and wr insns (-16). */
|
static char *v9a_asr_reg_names[] =
|
static char *v9a_asr_reg_names[] =
|
{
|
{
|
"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
|
"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
|
"softint", "tick_cmpr", "stick", "stick_cmpr"
|
"softint", "tick_cmpr", "stick", "stick_cmpr", "resv26",
|
|
"resv27", "cps"
|
};
|
};
|
|
|
/* Macros used to extract instruction fields. Not all fields have
|
/* Macros used to extract instruction fields. Not all fields have
|
macros defined here, only those which are actually used. */
|
macros defined here, only those which are actually used. */
|
|
|
#define X_RD(i) (((i) >> 25) & 0x1f)
|
#define X_RD(i) (((i) >> 25) & 0x1f)
|
#define X_RS1(i) (((i) >> 14) & 0x1f)
|
#define X_RS1(i) (((i) >> 14) & 0x1f)
|
#define X_LDST_I(i) (((i) >> 13) & 1)
|
#define X_LDST_I(i) (((i) >> 13) & 1)
|
#define X_ASI(i) (((i) >> 5) & 0xff)
|
#define X_ASI(i) (((i) >> 5) & 0xff)
|
#define X_RS2(i) (((i) >> 0) & 0x1f)
|
#define X_RS2(i) (((i) >> 0) & 0x1f)
|
|
#define X_RS3(i) (((i) >> 9) & 0x1f)
|
#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
|
#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
|
#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
|
#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
|
#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
|
#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
|
#define X_IMM22(i) X_DISP22 (i)
|
#define X_IMM22(i) X_DISP22 (i)
|
#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
|
#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
|
| Line 632... |
Line 634... |
case 'B': /* Double/even. */
|
case 'B': /* Double/even. */
|
case 'R': /* Quad/multiple of 4. */
|
case 'R': /* Quad/multiple of 4. */
|
fregx (X_RS2 (insn));
|
fregx (X_RS2 (insn));
|
break;
|
break;
|
|
|
|
case '4':
|
|
freg (X_RS3 (insn));
|
|
break;
|
|
case '5': /* Double/even. */
|
|
fregx (X_RS3 (insn));
|
|
break;
|
|
|
case 'g':
|
case 'g':
|
freg (X_RD (insn));
|
freg (X_RD (insn));
|
break;
|
break;
|
case 'H': /* Double/even. */
|
case 'H': /* Double/even. */
|
case 'J': /* Quad/multiple of 4. */
|
case 'J': /* Quad/multiple of 4. */
|
| Line 812... |
Line 821... |
else
|
else
|
(*info->fprintf_func) (stream, "%%reserved");
|
(*info->fprintf_func) (stream, "%%reserved");
|
break;
|
break;
|
|
|
case '/':
|
case '/':
|
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
|
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
|
(*info->fprintf_func) (stream, "%%reserved");
|
(*info->fprintf_func) (stream, "%%reserved");
|
else
|
else
|
(*info->fprintf_func) (stream, "%%%s",
|
(*info->fprintf_func) (stream, "%%%s",
|
v9a_asr_reg_names[X_RS1 (insn)-16]);
|
v9a_asr_reg_names[X_RS1 (insn)-16]);
|
break;
|
break;
|
|
|
case '_':
|
case '_':
|
if (X_RD (insn) < 16 || X_RD (insn) > 25)
|
if (X_RD (insn) < 16 || X_RD (insn) > 28)
|
(*info->fprintf_func) (stream, "%%reserved");
|
(*info->fprintf_func) (stream, "%%reserved");
|
else
|
else
|
(*info->fprintf_func) (stream, "%%%s",
|
(*info->fprintf_func) (stream, "%%%s",
|
v9a_asr_reg_names[X_RD (insn)-16]);
|
v9a_asr_reg_names[X_RD (insn)-16]);
|
break;
|
break;
|
| Line 880... |
Line 889... |
|
|
case 'F':
|
case 'F':
|
(*info->fprintf_func) (stream, "%%fsr");
|
(*info->fprintf_func) (stream, "%%fsr");
|
break;
|
break;
|
|
|
|
case '(':
|
|
(*info->fprintf_func) (stream, "%%efsr");
|
|
break;
|
|
|
case 'p':
|
case 'p':
|
(*info->fprintf_func) (stream, "%%psr");
|
(*info->fprintf_func) (stream, "%%psr");
|
break;
|
break;
|
|
|
case 'q':
|
case 'q':
|
