| Line 39... |
Line 39... |
#include <linux/stddef.h>
|
#include <linux/stddef.h>
|
#else
|
#else
|
#include <stddef.h>
|
#include <stddef.h>
|
#endif
|
#endif
|
|
|
const struct tilegx_opcode tilegx_opcodes[334] =
|
const struct tilegx_opcode tilegx_opcodes[336] =
|
{
|
{
|
{ "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
|
{ "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
|
{ { 0, }, { }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
| Line 98... |
Line 98... |
-1ULL,
|
-1ULL,
|
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
|
{ "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1,
|
|
{ { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
|
#ifndef DISASM_ONLY
|
|
{
|
|
0ULL,
|
|
0xfffff80000000000ULL,
|
|
0ULL,
|
|
0ULL,
|
|
0ULL
|
|
},
|
|
{
|
|
-1ULL,
|
|
0x1858000000000000ULL,
|
|
-1ULL,
|
|
-1ULL,
|
|
-1ULL
|
|
}
|
|
#endif
|
|
},
|
|
{ "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1,
|
|
{ { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
|
#ifndef DISASM_ONLY
|
|
{
|
|
0ULL,
|
|
0xfffff80000000000ULL,
|
|
0ULL,
|
|
0ULL,
|
|
0ULL
|
|
},
|
|
{
|
|
-1ULL,
|
|
0x18a0000000000000ULL,
|
|
-1ULL,
|
|
-1ULL,
|
|
-1ULL
|
|
}
|
|
#endif
|
|
},
|
{ "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
|
{ "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
|
{ { 6, 7 }, { 8, 9 }, { 10, 11 }, { 12, 13 }, { 0, } },
|
{ { 8, 9 }, { 6, 7 }, { 10, 11 }, { 12, 13 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 118... |
Line 156... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
|
{ "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
|
{ { 6, 0 }, { 8, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
|
{ { 8, 0 }, { 6, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00fc0ULL,
|
0xc00000007ff00fc0ULL,
|
0xfff807e000000000ULL,
|
0xfff807e000000000ULL,
|
0x0000000078000fc0ULL,
|
0x0000000078000fc0ULL,
|
| Line 137... |
Line 175... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
|
{ "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
|
{ { 6, 4 }, { 8, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 4 }, { 6, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc000000070000fc0ULL,
|
0xc000000070000fc0ULL,
|
0xf80007e000000000ULL,
|
0xf80007e000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 156... |
Line 194... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 289... |
Line 327... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 308... |
Line 346... |
0x41f8000004000000ULL
|
0x41f8000004000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 327... |
Line 365... |
0x41f8000000000000ULL
|
0x41f8000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 346... |
Line 384... |
0x43f8000004000000ULL
|
0x43f8000004000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 365... |
Line 403... |
0x43f8000000000000ULL
|
0x43f8000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 384... |
Line 422... |
0x83f8000000000000ULL
|
0x83f8000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 422... |
Line 460... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
|
{ "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 441... |
Line 479... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
|
{ "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x0000000078000000ULL,
|
0x0000000078000000ULL,
|
| Line 460... |
Line 498... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
|
{ "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc000000070000000ULL,
|
0xc000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 479... |
Line 517... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 498... |
Line 536... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
|
{ "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x0000000078000000ULL,
|
0x0000000078000000ULL,
|
| Line 517... |
Line 555... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
|
{ "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc000000070000000ULL,
|
0xc000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 536... |
Line 574... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
|
{ "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 555... |
Line 593... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
|
{ "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 574... |
Line 612... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
|
{ "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x0000000078000000ULL,
|
0x0000000078000000ULL,
|
| Line 593... |
Line 631... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
|
{ "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 612... |
Line 650... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
|
{ "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 631... |
Line 669... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
|
{ "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
|
{ { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007f000000ULL,
|
0xc00000007f000000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 650... |
Line 688... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
|
{ "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
|
{ { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007f000000ULL,
|
0xc00000007f000000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 669... |
Line 707... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
|
{ "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
|
{ { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007f000000ULL,
|
0xc00000007f000000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 688... |
Line 726... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 707... |
Line 745... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 726... |
Line 764... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 745... |
Line 783... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 764... |
Line 802... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
|
{ "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 783... |
Line 821... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
|
{ "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 802... |
Line 840... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
|
{ "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 821... |
Line 859... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
|
{ "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 840... |
Line 878... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
|
{ "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 859... |
Line 897... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
|
{ "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 878... |
Line 916... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 897... |
Line 935... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 916... |
Line 954... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 935... |
Line 973... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xffc0000000000000ULL,
|
0xffc0000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 954... |
Line 992... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
|
{ "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
|
{ { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
{ { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 973... |
Line 1011... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
|
{ "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 992... |
Line 1030... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
|
{ "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 1011... |
Line 1049... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
|
{ "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 1030... |
Line 1068... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
|
{ "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x0000000078000000ULL,
|
0x0000000078000000ULL,
|
| Line 1049... |
Line 1087... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
|
{ "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1068... |
Line 1106... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
|
{ "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1087... |
Line 1125... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
|
{ "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 1106... |
Line 1144... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
|
{ "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 1125... |
Line 1163... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
|
{ "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 1144... |
Line 1182... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
|
{ "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x0000000078000000ULL,
|
0x0000000078000000ULL,
|
| Line 1163... |
Line 1201... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
|
{ "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 1182... |
Line 1220... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
|
{ "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1201... |
Line 1239... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
|
{ "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 1220... |
Line 1258... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
|
{ "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1239... |
Line 1277... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
|
{ "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1258... |
Line 1296... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
|
{ "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1277... |
Line 1315... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
|
{ "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1296... |
Line 1334... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
|
{ "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1315... |
Line 1353... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
|
{ "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1334... |
Line 1372... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
|
{ "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1353... |
Line 1391... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
|
{ "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1372... |
Line 1410... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
|
{ "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1391... |
Line 1429... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
|
{ "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
|
{ { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
{ { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 1410... |
Line 1448... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
|
{ "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1429... |
Line 1467... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
|
{ "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1448... |
Line 1486... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
|
{ "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1467... |
Line 1505... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
|
{ "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1505... |
Line 1543... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
|
{ "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1524... |
Line 1562... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
|
{ "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1543... |
Line 1581... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
|
{ "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1562... |
Line 1600... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1581... |
Line 1619... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1600... |
Line 1638... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1619... |
Line 1657... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1638... |
Line 1676... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1657... |
Line 1695... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1676... |
Line 1714... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1695... |
Line 1733... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
|
{ "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1714... |
Line 1752... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1733... |
Line 1771... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1752... |
Line 1790... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1771... |
Line 1809... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1790... |
Line 1828... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1809... |
Line 1847... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1828... |
Line 1866... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1847... |
Line 1885... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
|
{ "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1866... |
Line 1904... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
|
{ "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1885... |
Line 1923... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
|
{ "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1942... |
Line 1980... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
|
{ "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1961... |
Line 1999... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
|
{ "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1980... |
Line 2018... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
|
{ "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1999... |
Line 2037... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
|
{ "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 2018... |
Line 2056... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
|
{ "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
|
{ { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
{ { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 2037... |
Line 2075... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
|
{ "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 2056... |
Line 2094... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
|
{ "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 2075... |
Line 2113... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
|
{ "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2113... |
Line 2151... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
|
{ "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2189... |
Line 2227... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
|
{ "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
|
{ { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2208... |
Line 2246... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
|
{ "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
|
{ { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2227... |
Line 2265... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
|
{ "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2246... |
Line 2284... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
|
{ "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2265... |
Line 2303... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
|
{ "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2284... |
Line 2322... |
0x8200000004000000ULL
|
0x8200000004000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
|
{ "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2303... |
Line 2341... |
0x4000000000000000ULL
|
0x4000000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2322... |
Line 2360... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
|
{ "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2341... |
Line 2379... |
0x4000000004000000ULL
|
0x4000000004000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2360... |
Line 2398... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
|
{ "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2379... |
Line 2417... |
0x4200000000000000ULL
|
0x4200000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2398... |
Line 2436... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
|
{ "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2417... |
Line 2455... |
0x4200000004000000ULL
|
0x4200000004000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2436... |
Line 2474... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
|
{ "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2455... |
Line 2493... |
0x8000000004000000ULL
|
0x8000000004000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2474... |
Line 2512... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
|
{ "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2493... |
Line 2531... |
0x8200000000000000ULL
|
0x8200000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2512... |
Line 2550... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2531... |
Line 2569... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
|
{ "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2550... |
Line 2588... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2569... |
Line 2607... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
|
{ "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2588... |
Line 2626... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
|
{ "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2607... |
Line 2645... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2626... |
Line 2664... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
|
{ "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2645... |
Line 2683... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2664... |
Line 2702... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
|
{ "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2683... |
Line 2721... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2702... |
Line 2740... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
|
{ "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2721... |
Line 2759... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2740... |
Line 2778... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
|
{ "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2759... |
Line 2797... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2778... |
Line 2816... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
|
{ "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2797... |
Line 2835... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2816... |
Line 2854... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2835... |
Line 2873... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
|
{ "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
|
{ { 0, }, { 8 }, { 0, }, { 12 }, { 0, } },
|
{ { 0, }, { 6 }, { 0, }, { 12 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2873... |
Line 2911... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
|
{ "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 8, 27 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 6, 27 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2892... |
Line 2930... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
|
{ "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
|
{ { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007f000000ULL,
|
0xc00000007f000000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 2911... |
Line 2949... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
|
{ "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 2930... |
Line 2968... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
|
{ "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 28, 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 28, 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2949... |
Line 2987... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
|
{ "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 2968... |
Line 3006... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
|
{ "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 2987... |
Line 3025... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
|
{ "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3006... |
Line 3044... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3025... |
Line 3063... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
|
{ "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3044... |
Line 3082... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
|
{ "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3063... |
Line 3101... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
|
{ "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3082... |
Line 3120... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
|
{ "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3101... |
Line 3139... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3120... |
Line 3158... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
|
{ "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3139... |
Line 3177... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
|
{ "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3158... |
Line 3196... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
|
{ "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3177... |
Line 3215... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
|
{ "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3196... |
Line 3234... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3215... |
Line 3253... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
|
{ "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3234... |
Line 3272... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
|
{ "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3253... |
Line 3291... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
|
{ "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3272... |
Line 3310... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
|
{ "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3291... |
Line 3329... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3310... |
Line 3348... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
|
{ "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3329... |
Line 3367... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
|
{ "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3348... |
Line 3386... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
|
{ "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3367... |
Line 3405... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
|
{ "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3424... |
Line 3462... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
|
{ "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3443... |
Line 3481... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
|
{ "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3462... |
Line 3500... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
|
{ "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3481... |
Line 3519... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
|
{ "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
|
{ { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
{ { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 3500... |
Line 3538... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
|
{ "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
|
{ { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
{ { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 3519... |
Line 3557... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
|
{ "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
|
{ { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
{ { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 3538... |
Line 3576... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
|
{ "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3557... |
Line 3595... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
|
{ "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3576... |
Line 3614... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
|
{ "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3595... |
Line 3633... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
|
{ "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc000000070000000ULL,
|
0xc000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3614... |
Line 3652... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
|
{ "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3633... |
Line 3671... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3652... |
Line 3690... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
|
{ "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3671... |
Line 3709... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3690... |
Line 3728... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
|
{ "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3709... |
Line 3747... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3728... |
Line 3766... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
|
{ "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3747... |
Line 3785... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
|
{ "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3766... |
Line 3804... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
|
{ "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3785... |
Line 3823... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
|
{ "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3804... |
Line 3842... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
|
{ "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3823... |
Line 3861... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
|
{ "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3842... |
Line 3880... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
|
{ "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 3861... |
Line 3899... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
|
{ "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3880... |
Line 3918... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
|
{ "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3899... |
Line 3937... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
|
{ "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3918... |
Line 3956... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
|
{ "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3937... |
Line 3975... |
0xc200000004000000ULL
|
0xc200000004000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
|
{ "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3975... |
Line 4013... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
|
{ "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4013... |
Line 4051... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
|
{ "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4070... |
Line 4108... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
|
{ "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4089... |
Line 4127... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
|
{ "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4127... |
Line 4165... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
|
{ "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4165... |
Line 4203... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
|
{ "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4222... |
Line 4260... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
|
{ "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 4241... |
Line 4279... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
|
{ "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 4260... |
Line 4298... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
|
{ "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4355... |
Line 4393... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
|
{ { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
{ { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 4374... |
Line 4412... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
|
{ { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
{ { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 4393... |
Line 4431... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
|
{ { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
{ { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 4412... |
Line 4450... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
|
{ { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
{ { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffff000ULL,
|
0xc00000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x00000000780ff000ULL,
|
0x00000000780ff000ULL,
|
| Line 4431... |
Line 4469... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
|
{ "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4450... |
Line 4488... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4469... |
Line 4507... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
|
{ "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4488... |
Line 4526... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4507... |
Line 4545... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4526... |
Line 4564... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4545... |
Line 4583... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4564... |
Line 4602... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4583... |
Line 4621... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4602... |
Line 4640... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4621... |
Line 4659... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4640... |
Line 4678... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4659... |
Line 4697... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4678... |
Line 4716... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
|
{ "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4697... |
Line 4735... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4716... |
Line 4754... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
|
{ "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4735... |
Line 4773... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
|
{ "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4754... |
Line 4792... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
|
{ "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4773... |
Line 4811... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
|
{ "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4792... |
Line 4830... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
|
{ "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4811... |
Line 4849... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4830... |
Line 4868... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
|
{ "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4849... |
Line 4887... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
|
{ "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4868... |
Line 4906... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
|
{ "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4887... |
Line 4925... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
|
{ "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4906... |
Line 4944... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
|
{ "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4925... |
Line 4963... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
|
{ "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4944... |
Line 4982... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4963... |
Line 5001... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
|
{ "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4982... |
Line 5020... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5001... |
Line 5039... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
|
{ "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5020... |
Line 5058... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5039... |
Line 5077... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5058... |
Line 5096... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
|
{ "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5077... |
Line 5115... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
|
{ "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5096... |
Line 5134... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5115... |
Line 5153... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
|
{ "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5134... |
Line 5172... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
|
{ "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5153... |
Line 5191... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5172... |
Line 5210... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
|
{ "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5191... |
Line 5229... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5210... |
Line 5248... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
|
{ "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5229... |
Line 5267... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
|
{ "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5248... |
Line 5286... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
|
{ "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5267... |
Line 5305... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
|
{ "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5286... |
Line 5324... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
|
{ "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5305... |
Line 5343... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5324... |
Line 5362... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
|
{ "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5343... |
Line 5381... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
|
{ "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5362... |
Line 5400... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
|
{ "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5381... |
Line 5419... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5400... |
Line 5438... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5419... |
Line 5457... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5438... |
Line 5476... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5457... |
Line 5495... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5476... |
Line 5514... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5495... |
Line 5533... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5514... |
Line 5552... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5533... |
Line 5571... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
|
{ "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5552... |
Line 5590... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
|
{ "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5571... |
Line 5609... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
|
{ "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5590... |
Line 5628... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
|
{ "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5609... |
Line 5647... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
|
{ "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5628... |
Line 5666... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
|
{ "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5647... |
Line 5685... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5666... |
Line 5704... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
|
{ "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5685... |
Line 5723... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5704... |
Line 5742... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
|
{ "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5723... |
Line 5761... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
|
{ "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5742... |
Line 5780... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
|
{ "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5761... |
Line 5799... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
|
{ "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5780... |
Line 5818... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
|
{ "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5799... |
Line 5837... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
|
{ "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5818... |
Line 5856... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
|
{ "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5837... |
Line 5875... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
|
{ "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5856... |
Line 5894... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
|
{ "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5875... |
Line 5913... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
|
{ "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
|
{ { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5894... |
Line 5932... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
|
{ "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5913... |
Line 5951... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
|
{ "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5932... |
Line 5970... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
|
{ "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5951... |
Line 5989... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5970... |
Line 6008... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
|
{ "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5989... |
Line 6027... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
|
{ "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6008... |
Line 6046... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6027... |
Line 6065... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
|
{ "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6046... |
Line 6084... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
|
{ "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6065... |
Line 6103... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
|
{ "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6084... |
Line 6122... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
|
{ "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6103... |
Line 6141... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
|
{ "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6122... |
Line 6160... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
|
{ "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6141... |
Line 6179... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
|
{ "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6160... |
Line 6198... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
|
{ "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6179... |
Line 6217... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
|
{ "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6198... |
Line 6236... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
|
{ "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6217... |
Line 6255... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
|
{ "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6236... |
Line 6274... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
|
{ "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6255... |
Line 6293... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
|
{ "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6274... |
Line 6312... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
|
{ "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6293... |
Line 6331... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
|
{ "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6312... |
Line 6350... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
|
{ "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6331... |
Line 6369... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
|
{ "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
|
{ { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
{ { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ffc0000ULL,
|
0xc00000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x00000000780c0000ULL,
|
0x00000000780c0000ULL,
|
| Line 6350... |
Line 6388... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
|
{ "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
|
{ { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0xc00000007ff00000ULL,
|
0xc00000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6670... |
Line 6708... |
BITFIELD(10, 2) /* index 931 */,
|
BITFIELD(10, 2) /* index 931 */,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_INFOL,
|
TILEGX_OPC_INFOL,
|
};
|
};
|
|
|
static const unsigned short decode_X1_fsm[1206] =
|
static const unsigned short decode_X1_fsm[1266] =
|
{
|
{
|
BITFIELD(53, 9) /* index 0 */,
|
BITFIELD(53, 9) /* index 0 */,
|
CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
|
CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
|
CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
|
CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
|
CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
|
CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
|
| Line 6716... |
Line 6754... |
TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
|
TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
|
TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
|
TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
|
TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
|
TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
|
TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
|
TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
|
TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
|
TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
|
CHILD(598), CHILD(663), CHILD(683), CHILD(688), CHILD(693), CHILD(698),
|
CHILD(598), CHILD(703), CHILD(723), CHILD(728), CHILD(753), CHILD(758),
|
CHILD(703), CHILD(708), CHILD(713), CHILD(718), TILEGX_OPC_NONE,
|
CHILD(763), CHILD(768), CHILD(773), CHILD(778), TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
| Line 6745... |
Line 6783... |
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
|
CHILD(723), CHILD(740), CHILD(772), CHILD(789), CHILD(1108), CHILD(1125),
|
CHILD(783), CHILD(800), CHILD(832), CHILD(849), CHILD(1168), CHILD(1185),
|
CHILD(1142), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
CHILD(1202), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
| Line 6760... |
Line 6798... |
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1159), TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1219), TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
| Line 6776... |
Line 6814... |
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1176), CHILD(1176), CHILD(1176),
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
|
CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
|
CHILD(1176),
|
CHILD(1236),
|
BITFIELD(37, 2) /* index 513 */,
|
BITFIELD(37, 2) /* index 513 */,
|
TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
|
TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
|
BITFIELD(39, 2) /* index 518 */,
|
BITFIELD(39, 2) /* index 518 */,
|
TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
|
TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
|
BITFIELD(41, 2) /* index 523 */,
|
BITFIELD(41, 2) /* index 523 */,
|
| Line 6849... |
Line 6887... |
TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
|
TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
|
BITFIELD(35, 2) /* index 643 */,
|
BITFIELD(35, 2) /* index 643 */,
|
TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
|
TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
|
TILEGX_OPC_PREFETCH_ADD_L2,
|
TILEGX_OPC_PREFETCH_ADD_L2,
|
BITFIELD(31, 2) /* index 648 */,
|
BITFIELD(31, 2) /* index 648 */,
|
TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(653),
|
CHILD(653), CHILD(653), CHILD(653), CHILD(673),
|
BITFIELD(33, 2) /* index 653 */,
|
BITFIELD(43, 2) /* index 653 */,
|
TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(658),
|
CHILD(658), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
|
BITFIELD(35, 2) /* index 658 */,
|
BITFIELD(45, 2) /* index 658 */,
|
TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
|
CHILD(663), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
|
TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
BITFIELD(47, 2) /* index 663 */,
|
BITFIELD(51, 2) /* index 663 */,
|
CHILD(668), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
|
CHILD(668), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
|
BITFIELD(49, 2) /* index 668 */,
|
TILEGX_OPC_LDNT2S_ADD,
|
TILEGX_OPC_LD4S_TLS, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
|
BITFIELD(31, 2) /* index 668 */,
|
TILEGX_OPC_LD4S_ADD,
|
TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(673),
|
|
BITFIELD(33, 2) /* index 673 */,
|
BITFIELD(33, 2) /* index 673 */,
|
TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(678),
|
CHILD(653), CHILD(653), CHILD(653), CHILD(678),
|
BITFIELD(35, 2) /* index 678 */,
|
BITFIELD(35, 2) /* index 678 */,
|
|
CHILD(653), CHILD(653), CHILD(653), CHILD(683),
|
|
BITFIELD(43, 2) /* index 683 */,
|
|
CHILD(688), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
BITFIELD(45, 2) /* index 688 */,
|
|
CHILD(693), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
BITFIELD(47, 2) /* index 693 */,
|
|
CHILD(698), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
BITFIELD(49, 2) /* index 698 */,
|
|
TILEGX_OPC_LD4S_TLS, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
|
|
BITFIELD(51, 2) /* index 703 */,
|
|
CHILD(708), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
|
|
TILEGX_OPC_LDNT2S_ADD,
|
|
BITFIELD(31, 2) /* index 708 */,
|
|
TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(713),
|
|
BITFIELD(33, 2) /* index 713 */,
|
|
TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(718),
|
|
BITFIELD(35, 2) /* index 718 */,
|
TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
|
TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
|
TILEGX_OPC_PREFETCH_ADD_L3,
|
TILEGX_OPC_PREFETCH_ADD_L3,
|
BITFIELD(51, 2) /* index 683 */,
|
BITFIELD(51, 2) /* index 723 */,
|
TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
|
TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
|
TILEGX_OPC_LDNT_ADD,
|
TILEGX_OPC_LDNT_ADD,
|
BITFIELD(51, 2) /* index 688 */,
|
BITFIELD(51, 2) /* index 728 */,
|
TILEGX_OPC_LD_ADD, TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
|
CHILD(733), TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
|
BITFIELD(51, 2) /* index 693 */,
|
BITFIELD(43, 2) /* index 733 */,
|
|
CHILD(738), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
|
|
BITFIELD(45, 2) /* index 738 */,
|
|
CHILD(743), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
|
|
BITFIELD(47, 2) /* index 743 */,
|
|
CHILD(748), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
|
|
BITFIELD(49, 2) /* index 748 */,
|
|
TILEGX_OPC_LD_TLS, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
|
|
BITFIELD(51, 2) /* index 753 */,
|
TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
|
TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
|
BITFIELD(51, 2) /* index 698 */,
|
BITFIELD(51, 2) /* index 758 */,
|
TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
|
TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
|
TILEGX_OPC_STNT_ADD,
|
TILEGX_OPC_STNT_ADD,
|
BITFIELD(51, 2) /* index 703 */,
|
BITFIELD(51, 2) /* index 763 */,
|
TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
|
TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
|
TILEGX_OPC_V1CMPLTSI,
|
TILEGX_OPC_V1CMPLTSI,
|
BITFIELD(51, 2) /* index 708 */,
|
BITFIELD(51, 2) /* index 768 */,
|
TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
|
TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
|
TILEGX_OPC_V2ADDI,
|
TILEGX_OPC_V2ADDI,
|
BITFIELD(51, 2) /* index 713 */,
|
BITFIELD(51, 2) /* index 773 */,
|
TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
|
TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
|
TILEGX_OPC_V2MAXSI,
|
TILEGX_OPC_V2MAXSI,
|
BITFIELD(51, 2) /* index 718 */,
|
BITFIELD(51, 2) /* index 778 */,
|
TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
BITFIELD(49, 4) /* index 723 */,
|
BITFIELD(49, 4) /* index 783 */,
|
TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
|
TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
|
TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
|
TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
|
TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
|
TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
|
TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
|
TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
|
TILEGX_OPC_DBLALIGN6,
|
TILEGX_OPC_DBLALIGN6,
|
BITFIELD(49, 4) /* index 740 */,
|
BITFIELD(49, 4) /* index 800 */,
|
TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
|
TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
|
TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
|
TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
|
TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
|
TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
|
TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
|
TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
|
CHILD(757), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
|
CHILD(817), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
|
BITFIELD(43, 2) /* index 757 */,
|
BITFIELD(43, 2) /* index 817 */,
|
TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(762),
|
TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(822),
|
BITFIELD(45, 2) /* index 762 */,
|
BITFIELD(45, 2) /* index 822 */,
|
TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(767),
|
TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(827),
|
BITFIELD(47, 2) /* index 767 */,
|
BITFIELD(47, 2) /* index 827 */,
|
TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
|
TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
|
BITFIELD(49, 4) /* index 772 */,
|
BITFIELD(49, 4) /* index 832 */,
|
TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
|
TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
|
TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
|
TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
|
TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
|
TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
|
TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
|
TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
|
TILEGX_OPC_STNT4,
|
TILEGX_OPC_STNT4,
|
BITFIELD(46, 7) /* index 789 */,
|
BITFIELD(46, 7) /* index 849 */,
|
TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
|
TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
|
TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
|
TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
|
TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
|
TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
|
TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
|
TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
|
TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
|
TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
|
TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
|
TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
|
TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
|
TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
|
TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
|
TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
|
TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
|
TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
|
TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(918), CHILD(927),
|
TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(978), CHILD(987),
|
CHILD(1006), CHILD(1090), CHILD(1099), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
CHILD(1066), CHILD(1150), CHILD(1159), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
|
TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
|
TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
|
TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
|
TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
|
TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
|
TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
|
TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
|
TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
|
TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
|
| Line 6948... |
Line 7014... |
TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
|
TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
|
TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
|
TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
|
TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
|
TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
|
TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
|
TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
|
TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
|
TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
|
BITFIELD(43, 3) /* index 918 */,
|
BITFIELD(43, 3) /* index 978 */,
|
TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
|
TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
|
TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
|
TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
|
BITFIELD(43, 3) /* index 927 */,
|
BITFIELD(43, 3) /* index 987 */,
|
CHILD(936), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
|
CHILD(996), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
|
TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(991),
|
TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(1051),
|
BITFIELD(31, 2) /* index 936 */,
|
BITFIELD(31, 2) /* index 996 */,
|
CHILD(941), CHILD(966), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
CHILD(1001), CHILD(1026), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
BITFIELD(33, 2) /* index 941 */,
|
BITFIELD(33, 2) /* index 1001 */,
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(946),
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1006),
|
BITFIELD(35, 2) /* index 946 */,
|
BITFIELD(35, 2) /* index 1006 */,
|
TILEGX_OPC_ILL, CHILD(951), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, CHILD(1011), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
BITFIELD(37, 2) /* index 951 */,
|
BITFIELD(37, 2) /* index 1011 */,
|
TILEGX_OPC_ILL, CHILD(956), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, CHILD(1016), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
BITFIELD(39, 2) /* index 956 */,
|
BITFIELD(39, 2) /* index 1016 */,
|
TILEGX_OPC_ILL, CHILD(961), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, CHILD(1021), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
BITFIELD(41, 2) /* index 961 */,
|
BITFIELD(41, 2) /* index 1021 */,
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
|
BITFIELD(33, 2) /* index 966 */,
|
BITFIELD(33, 2) /* index 1026 */,
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(971),
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1031),
|
BITFIELD(35, 2) /* index 971 */,
|
BITFIELD(35, 2) /* index 1031 */,
|
TILEGX_OPC_ILL, CHILD(976), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, CHILD(1036), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
BITFIELD(37, 2) /* index 976 */,
|
BITFIELD(37, 2) /* index 1036 */,
|
TILEGX_OPC_ILL, CHILD(981), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, CHILD(1041), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
BITFIELD(39, 2) /* index 981 */,
|
BITFIELD(39, 2) /* index 1041 */,
|
TILEGX_OPC_ILL, CHILD(986), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, CHILD(1046), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
|
BITFIELD(41, 2) /* index 986 */,
|
BITFIELD(41, 2) /* index 1046 */,
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
|
TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
|
BITFIELD(31, 2) /* index 991 */,
|
BITFIELD(31, 2) /* index 1051 */,
|
TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(996),
|
TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1056),
|
BITFIELD(33, 2) /* index 996 */,
|
BITFIELD(33, 2) /* index 1056 */,
|
TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1001),
|
TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1061),
|
BITFIELD(35, 2) /* index 1001 */,
|
BITFIELD(35, 2) /* index 1061 */,
|
TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
|
TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
|
TILEGX_OPC_PREFETCH_L1_FAULT,
|
TILEGX_OPC_PREFETCH_L1_FAULT,
|
BITFIELD(43, 3) /* index 1006 */,
|
BITFIELD(43, 3) /* index 1066 */,
|
CHILD(1015), CHILD(1030), CHILD(1045), CHILD(1060), CHILD(1075),
|
CHILD(1075), CHILD(1090), CHILD(1105), CHILD(1120), CHILD(1135),
|
TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
|
TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
|
BITFIELD(31, 2) /* index 1015 */,
|
BITFIELD(31, 2) /* index 1075 */,
|
TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1020),
|
TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1080),
|
BITFIELD(33, 2) /* index 1020 */,
|
BITFIELD(33, 2) /* index 1080 */,
|
TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1025),
|
TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1085),
|
BITFIELD(35, 2) /* index 1025 */,
|
BITFIELD(35, 2) /* index 1085 */,
|
TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
|
TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
|
BITFIELD(31, 2) /* index 1030 */,
|
BITFIELD(31, 2) /* index 1090 */,
|
TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1035),
|
TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1095),
|
BITFIELD(33, 2) /* index 1035 */,
|
BITFIELD(33, 2) /* index 1095 */,
|
TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1040),
|
TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1100),
|
BITFIELD(35, 2) /* index 1040 */,
|
BITFIELD(35, 2) /* index 1100 */,
|
TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
|
TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
|
TILEGX_OPC_PREFETCH_L2_FAULT,
|
TILEGX_OPC_PREFETCH_L2_FAULT,
|
BITFIELD(31, 2) /* index 1045 */,
|
BITFIELD(31, 2) /* index 1105 */,
|
TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1050),
|
TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1110),
|
BITFIELD(33, 2) /* index 1050 */,
|
BITFIELD(33, 2) /* index 1110 */,
|
TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1055),
|
TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1115),
|
BITFIELD(35, 2) /* index 1055 */,
|
BITFIELD(35, 2) /* index 1115 */,
|
TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
|
TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
|
BITFIELD(31, 2) /* index 1060 */,
|
BITFIELD(31, 2) /* index 1120 */,
|
TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1065),
|
TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1125),
|
BITFIELD(33, 2) /* index 1065 */,
|
BITFIELD(33, 2) /* index 1125 */,
|
TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1070),
|
TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1130),
|
BITFIELD(35, 2) /* index 1070 */,
|
BITFIELD(35, 2) /* index 1130 */,
|
TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
|
TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
|
TILEGX_OPC_PREFETCH_L3_FAULT,
|
TILEGX_OPC_PREFETCH_L3_FAULT,
|
BITFIELD(31, 2) /* index 1075 */,
|
BITFIELD(31, 2) /* index 1135 */,
|
TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1080),
|
TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1140),
|
BITFIELD(33, 2) /* index 1080 */,
|
BITFIELD(33, 2) /* index 1140 */,
|
TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1085),
|
TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1145),
|
BITFIELD(35, 2) /* index 1085 */,
|
BITFIELD(35, 2) /* index 1145 */,
|
TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
|
TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
|
BITFIELD(43, 3) /* index 1090 */,
|
BITFIELD(43, 3) /* index 1150 */,
|
TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
|
TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
|
TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
|
TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
|
BITFIELD(43, 3) /* index 1099 */,
|
BITFIELD(43, 3) /* index 1159 */,
|
TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
|
TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
|
TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
|
TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
|
BITFIELD(49, 4) /* index 1108 */,
|
BITFIELD(49, 4) /* index 1168 */,
|
TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
|
TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
|
TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
|
TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
|
TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
|
TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
|
TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
|
TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
|
TILEGX_OPC_V2CMPLTU,
|
TILEGX_OPC_V2CMPLTU,
|
BITFIELD(49, 4) /* index 1125 */,
|
BITFIELD(49, 4) /* index 1185 */,
|
TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
|
TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
|
TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
|
TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
|
TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
|
TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
|
TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
|
TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
|
TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
|
TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
|
BITFIELD(49, 4) /* index 1142 */,
|
BITFIELD(49, 4) /* index 1202 */,
|
TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
|
TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
|
TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
|
TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
|
TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
|
TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
|
TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
BITFIELD(49, 4) /* index 1159 */,
|
BITFIELD(49, 4) /* index 1219 */,
|
TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
|
TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
|
TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
|
TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
|
TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
|
TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
|
TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE,
|
TILEGX_OPC_NONE,
|
BITFIELD(31, 2) /* index 1176 */,
|
BITFIELD(31, 2) /* index 1236 */,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
CHILD(1181),
|
CHILD(1241),
|
BITFIELD(33, 2) /* index 1181 */,
|
BITFIELD(33, 2) /* index 1241 */,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
CHILD(1186),
|
CHILD(1246),
|
BITFIELD(35, 2) /* index 1186 */,
|
BITFIELD(35, 2) /* index 1246 */,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
CHILD(1191),
|
CHILD(1251),
|
BITFIELD(37, 2) /* index 1191 */,
|
BITFIELD(37, 2) /* index 1251 */,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
CHILD(1196),
|
CHILD(1256),
|
BITFIELD(39, 2) /* index 1196 */,
|
BITFIELD(39, 2) /* index 1256 */,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
CHILD(1201),
|
CHILD(1261),
|
BITFIELD(41, 2) /* index 1201 */,
|
BITFIELD(41, 2) /* index 1261 */,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
|
TILEGX_OPC_INFOL,
|
TILEGX_OPC_INFOL,
|
};
|
};
|
|
|
static const unsigned short decode_Y0_fsm[178] =
|
static const unsigned short decode_Y0_fsm[178] =
|
| Line 7326... |
Line 7392... |
create_Imm16_X1, get_Imm16_X1
|
create_Imm16_X1, get_Imm16_X1
|
},
|
},
|
{
|
{
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 0, 1, 0, 0,
|
6, 0, 0, 1, 0, 0,
|
create_Dest_X0, get_Dest_X0
|
create_Dest_X1, get_Dest_X1
|
},
|
},
|
{
|
{
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 1, 0, 0, 0,
|
6, 0, 1, 0, 0, 0,
|
create_SrcA_X0, get_SrcA_X0
|
create_SrcA_X1, get_SrcA_X1
|
},
|
},
|
{
|
{
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 0, 1, 0, 0,
|
6, 0, 0, 1, 0, 0,
|
create_Dest_X1, get_Dest_X1
|
create_Dest_X0, get_Dest_X0
|
},
|
},
|
{
|
{
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 1, 0, 0, 0,
|
6, 0, 1, 0, 0, 0,
|
create_SrcA_X1, get_SrcA_X1
|
create_SrcA_X0, get_SrcA_X0
|
},
|
},
|
{
|
{
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 0, 1, 0, 0,
|
6, 0, 0, 1, 0, 0,
|
create_Dest_Y0, get_Dest_Y0
|
create_Dest_Y0, get_Dest_Y0
|
