| Line 39... |
Line 39... |
#include <linux/stddef.h>
|
#include <linux/stddef.h>
|
#else
|
#else
|
#include <stddef.h>
|
#include <stddef.h>
|
#endif
|
#endif
|
|
|
const struct tilepro_opcode tilepro_opcodes[395] =
|
const struct tilepro_opcode tilepro_opcodes[397] =
|
{
|
{
|
{ "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
|
{ "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
|
{ { 0, }, { }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
| Line 136... |
Line 136... |
-1ULL,
|
-1ULL,
|
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
|
{ "lw_tls", TILEPRO_OPC_LW_TLS, 0x2, 3, TREG_ZERO, 1,
|
|
{ { 0, }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
|
#ifndef DISASM_ONLY
|
|
{
|
|
0ULL,
|
|
0xfffff80000000000ULL,
|
|
0ULL,
|
|
0ULL,
|
|
0ULL
|
|
},
|
|
{
|
|
-1ULL,
|
|
0x30d0000000000000ULL,
|
|
-1ULL,
|
|
-1ULL,
|
|
-1ULL
|
|
}
|
|
#endif
|
|
},
|
|
{ "lw_tls.sn", TILEPRO_OPC_LW_TLS_SN, 0x2, 3, TREG_SN, 1,
|
|
{ { 0, }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
|
#ifndef DISASM_ONLY
|
|
{
|
|
0ULL,
|
|
0xfffff80000000000ULL,
|
|
0ULL,
|
|
0ULL,
|
|
0ULL
|
|
},
|
|
{
|
|
-1ULL,
|
|
0x34d0000000000000ULL,
|
|
-1ULL,
|
|
-1ULL,
|
|
-1ULL
|
|
}
|
|
#endif
|
|
},
|
{ "move", TILEPRO_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
|
{ "move", TILEPRO_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
|
{ { 7, 8 }, { 9, 10 }, { 11, 12 }, { 13, 14 }, { 0, } },
|
{ { 9, 10 }, { 7, 8 }, { 11, 12 }, { 13, 14 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 156... |
Line 194... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "move.sn", TILEPRO_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1,
|
{ "move.sn", TILEPRO_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1,
|
{ { 7, 8 }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 175... |
Line 213... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "movei", TILEPRO_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
|
{ "movei", TILEPRO_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
|
{ { 7, 0 }, { 9, 1 }, { 11, 2 }, { 13, 3 }, { 0, } },
|
{ { 9, 0 }, { 7, 1 }, { 11, 2 }, { 13, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00fc0ULL,
|
0x800000007ff00fc0ULL,
|
0xfff807e000000000ULL,
|
0xfff807e000000000ULL,
|
0x8000000078000fc0ULL,
|
0x8000000078000fc0ULL,
|
| Line 194... |
Line 232... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "movei.sn", TILEPRO_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1,
|
{ "movei.sn", TILEPRO_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1,
|
{ { 7, 0 }, { 9, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 0 }, { 7, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00fc0ULL,
|
0x800000007ff00fc0ULL,
|
0xfff807e000000000ULL,
|
0xfff807e000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 213... |
Line 251... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "moveli", TILEPRO_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
|
{ "moveli", TILEPRO_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
|
{ { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 4 }, { 7, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000fc0ULL,
|
0x8000000070000fc0ULL,
|
0xf80007e000000000ULL,
|
0xf80007e000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 232... |
Line 270... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "moveli.sn", TILEPRO_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1,
|
{ "moveli.sn", TILEPRO_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1,
|
{ { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 4 }, { 7, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000fc0ULL,
|
0x8000000070000fc0ULL,
|
0xf80007e000000000ULL,
|
0xf80007e000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 251... |
Line 289... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "movelis", TILEPRO_OPC_MOVELIS, 0x3, 2, TREG_SN, 1,
|
{ "movelis", TILEPRO_OPC_MOVELIS, 0x3, 2, TREG_SN, 1,
|
{ { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 4 }, { 7, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000fc0ULL,
|
0x8000000070000fc0ULL,
|
0xf80007e000000000ULL,
|
0xf80007e000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 270... |
Line 308... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "prefetch", TILEPRO_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
|
{ "prefetch", TILEPRO_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 15 } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 15 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff81f80000000ULL,
|
0xfffff81f80000000ULL,
|
0ULL,
|
0ULL,
|
| Line 308... |
Line 346... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "add", TILEPRO_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
|
{ "add", TILEPRO_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 327... |
Line 365... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "add.sn", TILEPRO_OPC_ADD_SN, 0x3, 3, TREG_SN, 1,
|
{ "add.sn", TILEPRO_OPC_ADD_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 346... |
Line 384... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addb", TILEPRO_OPC_ADDB, 0x3, 3, TREG_ZERO, 1,
|
{ "addb", TILEPRO_OPC_ADDB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 365... |
Line 403... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addb.sn", TILEPRO_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1,
|
{ "addb.sn", TILEPRO_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 384... |
Line 422... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addbs_u", TILEPRO_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1,
|
{ "addbs_u", TILEPRO_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 403... |
Line 441... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addbs_u.sn", TILEPRO_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "addbs_u.sn", TILEPRO_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 422... |
Line 460... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addh", TILEPRO_OPC_ADDH, 0x3, 3, TREG_ZERO, 1,
|
{ "addh", TILEPRO_OPC_ADDH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 441... |
Line 479... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addh.sn", TILEPRO_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1,
|
{ "addh.sn", TILEPRO_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 460... |
Line 498... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addhs", TILEPRO_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1,
|
{ "addhs", TILEPRO_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 479... |
Line 517... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addhs.sn", TILEPRO_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1,
|
{ "addhs.sn", TILEPRO_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 498... |
Line 536... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addi", TILEPRO_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
|
{ "addi", TILEPRO_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x8000000078000000ULL,
|
0x8000000078000000ULL,
|
| Line 517... |
Line 555... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addi.sn", TILEPRO_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1,
|
{ "addi.sn", TILEPRO_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 536... |
Line 574... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addib", TILEPRO_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1,
|
{ "addib", TILEPRO_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 555... |
Line 593... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addib.sn", TILEPRO_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1,
|
{ "addib.sn", TILEPRO_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 574... |
Line 612... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addih", TILEPRO_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1,
|
{ "addih", TILEPRO_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 593... |
Line 631... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addih.sn", TILEPRO_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "addih.sn", TILEPRO_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 612... |
Line 650... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addli", TILEPRO_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
|
{ "addli", TILEPRO_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 4 }, { 7, 8, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000000ULL,
|
0x8000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 631... |
Line 669... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addli.sn", TILEPRO_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1,
|
{ "addli.sn", TILEPRO_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 4 }, { 7, 8, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000000ULL,
|
0x8000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 650... |
Line 688... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "addlis", TILEPRO_OPC_ADDLIS, 0x3, 3, TREG_SN, 1,
|
{ "addlis", TILEPRO_OPC_ADDLIS, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 4 }, { 7, 8, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000000ULL,
|
0x8000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 669... |
Line 707... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "adds", TILEPRO_OPC_ADDS, 0x3, 3, TREG_ZERO, 1,
|
{ "adds", TILEPRO_OPC_ADDS, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 688... |
Line 726... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "adds.sn", TILEPRO_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1,
|
{ "adds.sn", TILEPRO_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 707... |
Line 745... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "adiffb_u", TILEPRO_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1,
|
{ "adiffb_u", TILEPRO_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 726... |
Line 764... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "adiffb_u.sn", TILEPRO_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ "adiffb_u.sn", TILEPRO_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 745... |
Line 783... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "adiffh", TILEPRO_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1,
|
{ "adiffh", TILEPRO_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 764... |
Line 802... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "adiffh.sn", TILEPRO_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1,
|
{ "adiffh.sn", TILEPRO_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 783... |
Line 821... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "and", TILEPRO_OPC_AND, 0xf, 3, TREG_ZERO, 1,
|
{ "and", TILEPRO_OPC_AND, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 802... |
Line 840... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "and.sn", TILEPRO_OPC_AND_SN, 0x3, 3, TREG_SN, 1,
|
{ "and.sn", TILEPRO_OPC_AND_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 821... |
Line 859... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "andi", TILEPRO_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
|
{ "andi", TILEPRO_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x8000000078000000ULL,
|
0x8000000078000000ULL,
|
| Line 840... |
Line 878... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "andi.sn", TILEPRO_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1,
|
{ "andi.sn", TILEPRO_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 859... |
Line 897... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "auli", TILEPRO_OPC_AULI, 0x3, 3, TREG_ZERO, 1,
|
{ "auli", TILEPRO_OPC_AULI, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 4 }, { 7, 8, 5 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000000ULL,
|
0x8000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 878... |
Line 916... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "avgb_u", TILEPRO_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1,
|
{ "avgb_u", TILEPRO_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 897... |
Line 935... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "avgb_u.sn", TILEPRO_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ "avgb_u.sn", TILEPRO_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 916... |
Line 954... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "avgh", TILEPRO_OPC_AVGH, 0x1, 3, TREG_ZERO, 1,
|
{ "avgh", TILEPRO_OPC_AVGH, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 935... |
Line 973... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "avgh.sn", TILEPRO_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1,
|
{ "avgh.sn", TILEPRO_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 954... |
Line 992... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbns", TILEPRO_OPC_BBNS, 0x2, 2, TREG_ZERO, 1,
|
{ "bbns", TILEPRO_OPC_BBNS, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 973... |
Line 1011... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbns.sn", TILEPRO_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1,
|
{ "bbns.sn", TILEPRO_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 992... |
Line 1030... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbnst", TILEPRO_OPC_BBNST, 0x2, 2, TREG_ZERO, 1,
|
{ "bbnst", TILEPRO_OPC_BBNST, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1011... |
Line 1049... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbnst.sn", TILEPRO_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1,
|
{ "bbnst.sn", TILEPRO_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1030... |
Line 1068... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbs", TILEPRO_OPC_BBS, 0x2, 2, TREG_ZERO, 1,
|
{ "bbs", TILEPRO_OPC_BBS, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1049... |
Line 1087... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbs.sn", TILEPRO_OPC_BBS_SN, 0x2, 2, TREG_SN, 1,
|
{ "bbs.sn", TILEPRO_OPC_BBS_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1068... |
Line 1106... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbst", TILEPRO_OPC_BBST, 0x2, 2, TREG_ZERO, 1,
|
{ "bbst", TILEPRO_OPC_BBST, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1087... |
Line 1125... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bbst.sn", TILEPRO_OPC_BBST_SN, 0x2, 2, TREG_SN, 1,
|
{ "bbst.sn", TILEPRO_OPC_BBST_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1106... |
Line 1144... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgez", TILEPRO_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bgez", TILEPRO_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1125... |
Line 1163... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgez.sn", TILEPRO_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1,
|
{ "bgez.sn", TILEPRO_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1144... |
Line 1182... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgezt", TILEPRO_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bgezt", TILEPRO_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1163... |
Line 1201... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgezt.sn", TILEPRO_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1,
|
{ "bgezt.sn", TILEPRO_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1182... |
Line 1220... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgz", TILEPRO_OPC_BGZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bgz", TILEPRO_OPC_BGZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1201... |
Line 1239... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgz.sn", TILEPRO_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1,
|
{ "bgz.sn", TILEPRO_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1220... |
Line 1258... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgzt", TILEPRO_OPC_BGZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bgzt", TILEPRO_OPC_BGZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1239... |
Line 1277... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bgzt.sn", TILEPRO_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1,
|
{ "bgzt.sn", TILEPRO_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1258... |
Line 1296... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bitx", TILEPRO_OPC_BITX, 0x5, 2, TREG_ZERO, 1,
|
{ "bitx", TILEPRO_OPC_BITX, 0x5, 2, TREG_ZERO, 1,
|
{ { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 1277... |
Line 1315... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bitx.sn", TILEPRO_OPC_BITX_SN, 0x1, 2, TREG_SN, 1,
|
{ "bitx.sn", TILEPRO_OPC_BITX_SN, 0x1, 2, TREG_SN, 1,
|
{ { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1296... |
Line 1334... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blez", TILEPRO_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
|
{ "blez", TILEPRO_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1315... |
Line 1353... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blez.sn", TILEPRO_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1,
|
{ "blez.sn", TILEPRO_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1334... |
Line 1372... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blezt", TILEPRO_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
|
{ "blezt", TILEPRO_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1353... |
Line 1391... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blezt.sn", TILEPRO_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1,
|
{ "blezt.sn", TILEPRO_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1372... |
Line 1410... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blz", TILEPRO_OPC_BLZ, 0x2, 2, TREG_ZERO, 1,
|
{ "blz", TILEPRO_OPC_BLZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1391... |
Line 1429... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blz.sn", TILEPRO_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1,
|
{ "blz.sn", TILEPRO_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1410... |
Line 1448... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blzt", TILEPRO_OPC_BLZT, 0x2, 2, TREG_ZERO, 1,
|
{ "blzt", TILEPRO_OPC_BLZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1429... |
Line 1467... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "blzt.sn", TILEPRO_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1,
|
{ "blzt.sn", TILEPRO_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1448... |
Line 1486... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bnz", TILEPRO_OPC_BNZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bnz", TILEPRO_OPC_BNZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1467... |
Line 1505... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bnz.sn", TILEPRO_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1,
|
{ "bnz.sn", TILEPRO_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1486... |
Line 1524... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bnzt", TILEPRO_OPC_BNZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bnzt", TILEPRO_OPC_BNZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1505... |
Line 1543... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bnzt.sn", TILEPRO_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1,
|
{ "bnzt.sn", TILEPRO_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1524... |
Line 1562... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bytex", TILEPRO_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1,
|
{ "bytex", TILEPRO_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1,
|
{ { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 1543... |
Line 1581... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bytex.sn", TILEPRO_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1,
|
{ "bytex.sn", TILEPRO_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1,
|
{ { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1562... |
Line 1600... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bz", TILEPRO_OPC_BZ, 0x2, 2, TREG_ZERO, 1,
|
{ "bz", TILEPRO_OPC_BZ, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1581... |
Line 1619... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bz.sn", TILEPRO_OPC_BZ_SN, 0x2, 2, TREG_SN, 1,
|
{ "bz.sn", TILEPRO_OPC_BZ_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1600... |
Line 1638... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bzt", TILEPRO_OPC_BZT, 0x2, 2, TREG_ZERO, 1,
|
{ "bzt", TILEPRO_OPC_BZT, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1619... |
Line 1657... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "bzt.sn", TILEPRO_OPC_BZT_SN, 0x2, 2, TREG_SN, 1,
|
{ "bzt.sn", TILEPRO_OPC_BZT_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8, 20 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfc00000780000000ULL,
|
0xfc00000780000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1638... |
Line 1676... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "clz", TILEPRO_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
|
{ "clz", TILEPRO_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
|
{ { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 1657... |
Line 1695... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "clz.sn", TILEPRO_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1,
|
{ "clz.sn", TILEPRO_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1,
|
{ { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1676... |
Line 1714... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "crc32_32", TILEPRO_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
|
{ "crc32_32", TILEPRO_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1695... |
Line 1733... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "crc32_32.sn", TILEPRO_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1,
|
{ "crc32_32.sn", TILEPRO_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1714... |
Line 1752... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "crc32_8", TILEPRO_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
|
{ "crc32_8", TILEPRO_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1733... |
Line 1771... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "crc32_8.sn", TILEPRO_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1,
|
{ "crc32_8.sn", TILEPRO_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1752... |
Line 1790... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ctz", TILEPRO_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
|
{ "ctz", TILEPRO_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
|
{ { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 1771... |
Line 1809... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ctz.sn", TILEPRO_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1,
|
{ "ctz.sn", TILEPRO_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1,
|
{ { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1809... |
Line 1847... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dtlbpr", TILEPRO_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
|
{ "dtlbpr", TILEPRO_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfff80000000000ULL,
|
0xfbfff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1828... |
Line 1866... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dword_align", TILEPRO_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1,
|
{ "dword_align", TILEPRO_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1847... |
Line 1885... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "dword_align.sn", TILEPRO_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1,
|
{ "dword_align.sn", TILEPRO_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 1866... |
Line 1904... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "finv", TILEPRO_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
|
{ "finv", TILEPRO_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfff80000000000ULL,
|
0xfbfff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1885... |
Line 1923... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "flush", TILEPRO_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
|
{ "flush", TILEPRO_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfff80000000000ULL,
|
0xfbfff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1923... |
Line 1961... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "icoh", TILEPRO_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
|
{ "icoh", TILEPRO_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfff80000000000ULL,
|
0xfbfff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1961... |
Line 1999... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "inthb", TILEPRO_OPC_INTHB, 0x3, 3, TREG_ZERO, 1,
|
{ "inthb", TILEPRO_OPC_INTHB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1980... |
Line 2018... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "inthb.sn", TILEPRO_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1,
|
{ "inthb.sn", TILEPRO_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 1999... |
Line 2037... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "inthh", TILEPRO_OPC_INTHH, 0x3, 3, TREG_ZERO, 1,
|
{ "inthh", TILEPRO_OPC_INTHH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2018... |
Line 2056... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "inthh.sn", TILEPRO_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1,
|
{ "inthh.sn", TILEPRO_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2037... |
Line 2075... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "intlb", TILEPRO_OPC_INTLB, 0x3, 3, TREG_ZERO, 1,
|
{ "intlb", TILEPRO_OPC_INTLB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2056... |
Line 2094... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "intlb.sn", TILEPRO_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1,
|
{ "intlb.sn", TILEPRO_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2075... |
Line 2113... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "intlh", TILEPRO_OPC_INTLH, 0x3, 3, TREG_ZERO, 1,
|
{ "intlh", TILEPRO_OPC_INTLH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2094... |
Line 2132... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "intlh.sn", TILEPRO_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1,
|
{ "intlh.sn", TILEPRO_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2113... |
Line 2151... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "inv", TILEPRO_OPC_INV, 0x2, 1, TREG_ZERO, 1,
|
{ "inv", TILEPRO_OPC_INV, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfff80000000000ULL,
|
0xfbfff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2189... |
Line 2227... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jalr", TILEPRO_OPC_JALR, 0x2, 1, TREG_LR, 1,
|
{ "jalr", TILEPRO_OPC_JALR, 0x2, 1, TREG_LR, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfe000000000000ULL,
|
0xfbfe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2208... |
Line 2246... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jalrp", TILEPRO_OPC_JALRP, 0x2, 1, TREG_LR, 1,
|
{ "jalrp", TILEPRO_OPC_JALRP, 0x2, 1, TREG_LR, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfe000000000000ULL,
|
0xfbfe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2265... |
Line 2303... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jr", TILEPRO_OPC_JR, 0x2, 1, TREG_ZERO, 1,
|
{ "jr", TILEPRO_OPC_JR, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfe000000000000ULL,
|
0xfbfe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2284... |
Line 2322... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "jrp", TILEPRO_OPC_JRP, 0x2, 1, TREG_ZERO, 1,
|
{ "jrp", TILEPRO_OPC_JRP, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfe000000000000ULL,
|
0xfbfe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2303... |
Line 2341... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lb", TILEPRO_OPC_LB, 0x12, 2, TREG_ZERO, 1,
|
{ "lb", TILEPRO_OPC_LB, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 23, 15 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2322... |
Line 2360... |
0x8000000000000000ULL
|
0x8000000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lb.sn", TILEPRO_OPC_LB_SN, 0x2, 2, TREG_SN, 1,
|
{ "lb.sn", TILEPRO_OPC_LB_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2341... |
Line 2379... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lb_u", TILEPRO_OPC_LB_U, 0x12, 2, TREG_ZERO, 1,
|
{ "lb_u", TILEPRO_OPC_LB_U, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 23, 15 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2360... |
Line 2398... |
0x8100000000000000ULL
|
0x8100000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lb_u.sn", TILEPRO_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1,
|
{ "lb_u.sn", TILEPRO_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2379... |
Line 2417... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lbadd", TILEPRO_OPC_LBADD, 0x2, 3, TREG_ZERO, 1,
|
{ "lbadd", TILEPRO_OPC_LBADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2398... |
Line 2436... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lbadd.sn", TILEPRO_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1,
|
{ "lbadd.sn", TILEPRO_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2417... |
Line 2455... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lbadd_u", TILEPRO_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1,
|
{ "lbadd_u", TILEPRO_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2436... |
Line 2474... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lbadd_u.sn", TILEPRO_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1,
|
{ "lbadd_u.sn", TILEPRO_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2455... |
Line 2493... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lh", TILEPRO_OPC_LH, 0x12, 2, TREG_ZERO, 1,
|
{ "lh", TILEPRO_OPC_LH, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 23, 15 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2474... |
Line 2512... |
0x8200000000000000ULL
|
0x8200000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lh.sn", TILEPRO_OPC_LH_SN, 0x2, 2, TREG_SN, 1,
|
{ "lh.sn", TILEPRO_OPC_LH_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2493... |
Line 2531... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lh_u", TILEPRO_OPC_LH_U, 0x12, 2, TREG_ZERO, 1,
|
{ "lh_u", TILEPRO_OPC_LH_U, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 23, 15 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2512... |
Line 2550... |
0x8300000000000000ULL
|
0x8300000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lh_u.sn", TILEPRO_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1,
|
{ "lh_u.sn", TILEPRO_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2531... |
Line 2569... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lhadd", TILEPRO_OPC_LHADD, 0x2, 3, TREG_ZERO, 1,
|
{ "lhadd", TILEPRO_OPC_LHADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2550... |
Line 2588... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lhadd.sn", TILEPRO_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1,
|
{ "lhadd.sn", TILEPRO_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2569... |
Line 2607... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lhadd_u", TILEPRO_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1,
|
{ "lhadd_u", TILEPRO_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2588... |
Line 2626... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lhadd_u.sn", TILEPRO_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1,
|
{ "lhadd_u.sn", TILEPRO_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2607... |
Line 2645... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lnk", TILEPRO_OPC_LNK, 0x2, 1, TREG_ZERO, 1,
|
{ "lnk", TILEPRO_OPC_LNK, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2626... |
Line 2664... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lnk.sn", TILEPRO_OPC_LNK_SN, 0x2, 1, TREG_SN, 1,
|
{ "lnk.sn", TILEPRO_OPC_LNK_SN, 0x2, 1, TREG_SN, 1,
|
{ { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2645... |
Line 2683... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lw", TILEPRO_OPC_LW, 0x12, 2, TREG_ZERO, 1,
|
{ "lw", TILEPRO_OPC_LW, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 23, 15 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2664... |
Line 2702... |
0x8400000000000000ULL
|
0x8400000000000000ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lw.sn", TILEPRO_OPC_LW_SN, 0x2, 2, TREG_SN, 1,
|
{ "lw.sn", TILEPRO_OPC_LW_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2683... |
Line 2721... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lw_na", TILEPRO_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1,
|
{ "lw_na", TILEPRO_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2702... |
Line 2740... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lw_na.sn", TILEPRO_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1,
|
{ "lw_na.sn", TILEPRO_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2721... |
Line 2759... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lwadd", TILEPRO_OPC_LWADD, 0x2, 3, TREG_ZERO, 1,
|
{ "lwadd", TILEPRO_OPC_LWADD, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2740... |
Line 2778... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lwadd.sn", TILEPRO_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1,
|
{ "lwadd.sn", TILEPRO_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2759... |
Line 2797... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lwadd_na", TILEPRO_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1,
|
{ "lwadd_na", TILEPRO_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2778... |
Line 2816... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "lwadd_na.sn", TILEPRO_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1,
|
{ "lwadd_na.sn", TILEPRO_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1,
|
{ { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 24, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2797... |
Line 2835... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxb_u", TILEPRO_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1,
|
{ "maxb_u", TILEPRO_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2816... |
Line 2854... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxb_u.sn", TILEPRO_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "maxb_u.sn", TILEPRO_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2835... |
Line 2873... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxh", TILEPRO_OPC_MAXH, 0x3, 3, TREG_ZERO, 1,
|
{ "maxh", TILEPRO_OPC_MAXH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2854... |
Line 2892... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxh.sn", TILEPRO_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1,
|
{ "maxh.sn", TILEPRO_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2873... |
Line 2911... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxib_u", TILEPRO_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1,
|
{ "maxib_u", TILEPRO_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2892... |
Line 2930... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxib_u.sn", TILEPRO_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "maxib_u.sn", TILEPRO_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2911... |
Line 2949... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxih", TILEPRO_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1,
|
{ "maxih", TILEPRO_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2930... |
Line 2968... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "maxih.sn", TILEPRO_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "maxih.sn", TILEPRO_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2968... |
Line 3006... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mfspr", TILEPRO_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
|
{ "mfspr", TILEPRO_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 25 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 25 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbf8000000000000ULL,
|
0xfbf8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 2987... |
Line 3025... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minb_u", TILEPRO_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1,
|
{ "minb_u", TILEPRO_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3006... |
Line 3044... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minb_u.sn", TILEPRO_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "minb_u.sn", TILEPRO_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3025... |
Line 3063... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minh", TILEPRO_OPC_MINH, 0x3, 3, TREG_ZERO, 1,
|
{ "minh", TILEPRO_OPC_MINH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3044... |
Line 3082... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minh.sn", TILEPRO_OPC_MINH_SN, 0x3, 3, TREG_SN, 1,
|
{ "minh.sn", TILEPRO_OPC_MINH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3063... |
Line 3101... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minib_u", TILEPRO_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1,
|
{ "minib_u", TILEPRO_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3082... |
Line 3120... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minib_u.sn", TILEPRO_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "minib_u.sn", TILEPRO_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3101... |
Line 3139... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minih", TILEPRO_OPC_MINIH, 0x3, 3, TREG_ZERO, 1,
|
{ "minih", TILEPRO_OPC_MINIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3120... |
Line 3158... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "minih.sn", TILEPRO_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "minih.sn", TILEPRO_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3139... |
Line 3177... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mm", TILEPRO_OPC_MM, 0x3, 5, TREG_ZERO, 1,
|
{ "mm", TILEPRO_OPC_MM, 0x3, 5, TREG_ZERO, 1,
|
{ { 7, 8, 16, 26, 27 }, { 9, 10, 17, 28, 29 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16, 26, 27 }, { 7, 8, 17, 28, 29 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x8000000070000000ULL,
|
0x8000000070000000ULL,
|
0xf800000000000000ULL,
|
0xf800000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3158... |
Line 3196... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mnz", TILEPRO_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
|
{ "mnz", TILEPRO_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3177... |
Line 3215... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mnz.sn", TILEPRO_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1,
|
{ "mnz.sn", TILEPRO_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3196... |
Line 3234... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mnzb", TILEPRO_OPC_MNZB, 0x3, 3, TREG_ZERO, 1,
|
{ "mnzb", TILEPRO_OPC_MNZB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3215... |
Line 3253... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mnzb.sn", TILEPRO_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1,
|
{ "mnzb.sn", TILEPRO_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3234... |
Line 3272... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mnzh", TILEPRO_OPC_MNZH, 0x3, 3, TREG_ZERO, 1,
|
{ "mnzh", TILEPRO_OPC_MNZH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3253... |
Line 3291... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mnzh.sn", TILEPRO_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1,
|
{ "mnzh.sn", TILEPRO_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3272... |
Line 3310... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mtspr", TILEPRO_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
|
{ "mtspr", TILEPRO_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 30, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 30, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbf8000000000000ULL,
|
0xfbf8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 3291... |
Line 3329... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhh_ss", TILEPRO_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1,
|
{ "mulhh_ss", TILEPRO_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3310... |
Line 3348... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhh_ss.sn", TILEPRO_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhh_ss.sn", TILEPRO_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3329... |
Line 3367... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhh_su", TILEPRO_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhh_su", TILEPRO_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3348... |
Line 3386... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhh_su.sn", TILEPRO_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhh_su.sn", TILEPRO_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3367... |
Line 3405... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhh_uu", TILEPRO_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1,
|
{ "mulhh_uu", TILEPRO_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3386... |
Line 3424... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhh_uu.sn", TILEPRO_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhh_uu.sn", TILEPRO_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3405... |
Line 3443... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhha_ss", TILEPRO_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1,
|
{ "mulhha_ss", TILEPRO_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3424... |
Line 3462... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhha_ss.sn", TILEPRO_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhha_ss.sn", TILEPRO_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3443... |
Line 3481... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhha_su", TILEPRO_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhha_su", TILEPRO_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3462... |
Line 3500... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhha_su.sn", TILEPRO_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhha_su.sn", TILEPRO_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3481... |
Line 3519... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhha_uu", TILEPRO_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1,
|
{ "mulhha_uu", TILEPRO_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3500... |
Line 3538... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhha_uu.sn", TILEPRO_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhha_uu.sn", TILEPRO_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3519... |
Line 3557... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhhsa_uu", TILEPRO_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhhsa_uu", TILEPRO_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3538... |
Line 3576... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhhsa_uu.sn", TILEPRO_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhhsa_uu.sn", TILEPRO_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3557... |
Line 3595... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_ss", TILEPRO_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhl_ss", TILEPRO_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3576... |
Line 3614... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_ss.sn", TILEPRO_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhl_ss.sn", TILEPRO_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3595... |
Line 3633... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_su", TILEPRO_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhl_su", TILEPRO_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3614... |
Line 3652... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_su.sn", TILEPRO_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhl_su.sn", TILEPRO_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3633... |
Line 3671... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_us", TILEPRO_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhl_us", TILEPRO_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3652... |
Line 3690... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_us.sn", TILEPRO_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhl_us.sn", TILEPRO_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3671... |
Line 3709... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_uu", TILEPRO_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhl_uu", TILEPRO_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3690... |
Line 3728... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhl_uu.sn", TILEPRO_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhl_uu.sn", TILEPRO_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3709... |
Line 3747... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_ss", TILEPRO_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhla_ss", TILEPRO_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3728... |
Line 3766... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_ss.sn", TILEPRO_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhla_ss.sn", TILEPRO_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3747... |
Line 3785... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_su", TILEPRO_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhla_su", TILEPRO_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3766... |
Line 3804... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_su.sn", TILEPRO_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhla_su.sn", TILEPRO_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3785... |
Line 3823... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_us", TILEPRO_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhla_us", TILEPRO_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3804... |
Line 3842... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_us.sn", TILEPRO_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhla_us.sn", TILEPRO_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3823... |
Line 3861... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_uu", TILEPRO_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulhla_uu", TILEPRO_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3842... |
Line 3880... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhla_uu.sn", TILEPRO_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhla_uu.sn", TILEPRO_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3861... |
Line 3899... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhlsa_uu", TILEPRO_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1,
|
{ "mulhlsa_uu", TILEPRO_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3880... |
Line 3918... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulhlsa_uu.sn", TILEPRO_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulhlsa_uu.sn", TILEPRO_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3899... |
Line 3937... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulll_ss", TILEPRO_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1,
|
{ "mulll_ss", TILEPRO_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3918... |
Line 3956... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulll_ss.sn", TILEPRO_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulll_ss.sn", TILEPRO_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3937... |
Line 3975... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulll_su", TILEPRO_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulll_su", TILEPRO_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3956... |
Line 3994... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulll_su.sn", TILEPRO_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulll_su.sn", TILEPRO_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 3975... |
Line 4013... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulll_uu", TILEPRO_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1,
|
{ "mulll_uu", TILEPRO_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 3994... |
Line 4032... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulll_uu.sn", TILEPRO_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulll_uu.sn", TILEPRO_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4013... |
Line 4051... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mullla_ss", TILEPRO_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1,
|
{ "mullla_ss", TILEPRO_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4032... |
Line 4070... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mullla_ss.sn", TILEPRO_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ "mullla_ss.sn", TILEPRO_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4051... |
Line 4089... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mullla_su", TILEPRO_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1,
|
{ "mullla_su", TILEPRO_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4070... |
Line 4108... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mullla_su.sn", TILEPRO_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mullla_su.sn", TILEPRO_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4089... |
Line 4127... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mullla_uu", TILEPRO_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1,
|
{ "mullla_uu", TILEPRO_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4108... |
Line 4146... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mullla_uu.sn", TILEPRO_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mullla_uu.sn", TILEPRO_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4127... |
Line 4165... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulllsa_uu", TILEPRO_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1,
|
{ "mulllsa_uu", TILEPRO_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4146... |
Line 4184... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mulllsa_uu.sn", TILEPRO_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ "mulllsa_uu.sn", TILEPRO_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4165... |
Line 4203... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mvnz", TILEPRO_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1,
|
{ "mvnz", TILEPRO_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4184... |
Line 4222... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mvnz.sn", TILEPRO_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1,
|
{ "mvnz.sn", TILEPRO_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4203... |
Line 4241... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mvz", TILEPRO_OPC_MVZ, 0x5, 3, TREG_ZERO, 1,
|
{ "mvz", TILEPRO_OPC_MVZ, 0x5, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4222... |
Line 4260... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mvz.sn", TILEPRO_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1,
|
{ "mvz.sn", TILEPRO_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4241... |
Line 4279... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mz", TILEPRO_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
|
{ "mz", TILEPRO_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4260... |
Line 4298... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mz.sn", TILEPRO_OPC_MZ_SN, 0x3, 3, TREG_SN, 1,
|
{ "mz.sn", TILEPRO_OPC_MZ_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4279... |
Line 4317... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mzb", TILEPRO_OPC_MZB, 0x3, 3, TREG_ZERO, 1,
|
{ "mzb", TILEPRO_OPC_MZB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4298... |
Line 4336... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mzb.sn", TILEPRO_OPC_MZB_SN, 0x3, 3, TREG_SN, 1,
|
{ "mzb.sn", TILEPRO_OPC_MZB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4317... |
Line 4355... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mzh", TILEPRO_OPC_MZH, 0x3, 3, TREG_ZERO, 1,
|
{ "mzh", TILEPRO_OPC_MZH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4336... |
Line 4374... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "mzh.sn", TILEPRO_OPC_MZH_SN, 0x3, 3, TREG_SN, 1,
|
{ "mzh.sn", TILEPRO_OPC_MZH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4393... |
Line 4431... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "nor", TILEPRO_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
|
{ "nor", TILEPRO_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4412... |
Line 4450... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "nor.sn", TILEPRO_OPC_NOR_SN, 0x3, 3, TREG_SN, 1,
|
{ "nor.sn", TILEPRO_OPC_NOR_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4431... |
Line 4469... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "or", TILEPRO_OPC_OR, 0xf, 3, TREG_ZERO, 1,
|
{ "or", TILEPRO_OPC_OR, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4450... |
Line 4488... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "or.sn", TILEPRO_OPC_OR_SN, 0x3, 3, TREG_SN, 1,
|
{ "or.sn", TILEPRO_OPC_OR_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4469... |
Line 4507... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ori", TILEPRO_OPC_ORI, 0xf, 3, TREG_ZERO, 1,
|
{ "ori", TILEPRO_OPC_ORI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x8000000078000000ULL,
|
0x8000000078000000ULL,
|
| Line 4488... |
Line 4526... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "ori.sn", TILEPRO_OPC_ORI_SN, 0x3, 3, TREG_SN, 1,
|
{ "ori.sn", TILEPRO_OPC_ORI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4507... |
Line 4545... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packbs_u", TILEPRO_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1,
|
{ "packbs_u", TILEPRO_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4526... |
Line 4564... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packbs_u.sn", TILEPRO_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "packbs_u.sn", TILEPRO_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4545... |
Line 4583... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packhb", TILEPRO_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1,
|
{ "packhb", TILEPRO_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4564... |
Line 4602... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packhb.sn", TILEPRO_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1,
|
{ "packhb.sn", TILEPRO_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4583... |
Line 4621... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packhs", TILEPRO_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1,
|
{ "packhs", TILEPRO_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4602... |
Line 4640... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packhs.sn", TILEPRO_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1,
|
{ "packhs.sn", TILEPRO_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4621... |
Line 4659... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packlb", TILEPRO_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1,
|
{ "packlb", TILEPRO_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4640... |
Line 4678... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "packlb.sn", TILEPRO_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1,
|
{ "packlb.sn", TILEPRO_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4659... |
Line 4697... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "pcnt", TILEPRO_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
|
{ "pcnt", TILEPRO_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
|
{ { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 4678... |
Line 4716... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "pcnt.sn", TILEPRO_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1,
|
{ "pcnt.sn", TILEPRO_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1,
|
{ { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4697... |
Line 4735... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "rl", TILEPRO_OPC_RL, 0xf, 3, TREG_ZERO, 1,
|
{ "rl", TILEPRO_OPC_RL, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4716... |
Line 4754... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "rl.sn", TILEPRO_OPC_RL_SN, 0x3, 3, TREG_SN, 1,
|
{ "rl.sn", TILEPRO_OPC_RL_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4735... |
Line 4773... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "rli", TILEPRO_OPC_RLI, 0xf, 3, TREG_ZERO, 1,
|
{ "rli", TILEPRO_OPC_RLI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0x80000000780e0000ULL,
|
0x80000000780e0000ULL,
|
| Line 4754... |
Line 4792... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "rli.sn", TILEPRO_OPC_RLI_SN, 0x3, 3, TREG_SN, 1,
|
{ "rli.sn", TILEPRO_OPC_RLI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4773... |
Line 4811... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "s1a", TILEPRO_OPC_S1A, 0xf, 3, TREG_ZERO, 1,
|
{ "s1a", TILEPRO_OPC_S1A, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4792... |
Line 4830... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "s1a.sn", TILEPRO_OPC_S1A_SN, 0x3, 3, TREG_SN, 1,
|
{ "s1a.sn", TILEPRO_OPC_S1A_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4811... |
Line 4849... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "s2a", TILEPRO_OPC_S2A, 0xf, 3, TREG_ZERO, 1,
|
{ "s2a", TILEPRO_OPC_S2A, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4830... |
Line 4868... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "s2a.sn", TILEPRO_OPC_S2A_SN, 0x3, 3, TREG_SN, 1,
|
{ "s2a.sn", TILEPRO_OPC_S2A_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4849... |
Line 4887... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "s3a", TILEPRO_OPC_S3A, 0xf, 3, TREG_ZERO, 1,
|
{ "s3a", TILEPRO_OPC_S3A, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 4868... |
Line 4906... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "s3a.sn", TILEPRO_OPC_S3A_SN, 0x3, 3, TREG_SN, 1,
|
{ "s3a.sn", TILEPRO_OPC_S3A_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 4887... |
Line 4925... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadab_u", TILEPRO_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1,
|
{ "sadab_u", TILEPRO_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4906... |
Line 4944... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadab_u.sn", TILEPRO_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ "sadab_u.sn", TILEPRO_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4925... |
Line 4963... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadah", TILEPRO_OPC_SADAH, 0x1, 3, TREG_ZERO, 1,
|
{ "sadah", TILEPRO_OPC_SADAH, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4944... |
Line 4982... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadah.sn", TILEPRO_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1,
|
{ "sadah.sn", TILEPRO_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4963... |
Line 5001... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadah_u", TILEPRO_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1,
|
{ "sadah_u", TILEPRO_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 4982... |
Line 5020... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadah_u.sn", TILEPRO_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1,
|
{ "sadah_u.sn", TILEPRO_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1,
|
{ { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5001... |
Line 5039... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadb_u", TILEPRO_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1,
|
{ "sadb_u", TILEPRO_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5020... |
Line 5058... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadb_u.sn", TILEPRO_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ "sadb_u.sn", TILEPRO_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5039... |
Line 5077... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadh", TILEPRO_OPC_SADH, 0x1, 3, TREG_ZERO, 1,
|
{ "sadh", TILEPRO_OPC_SADH, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5058... |
Line 5096... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadh.sn", TILEPRO_OPC_SADH_SN, 0x1, 3, TREG_SN, 1,
|
{ "sadh.sn", TILEPRO_OPC_SADH_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5077... |
Line 5115... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadh_u", TILEPRO_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1,
|
{ "sadh_u", TILEPRO_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5096... |
Line 5134... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sadh_u.sn", TILEPRO_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1,
|
{ "sadh_u.sn", TILEPRO_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 5115... |
Line 5153... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sb", TILEPRO_OPC_SB, 0x12, 2, TREG_ZERO, 1,
|
{ "sb", TILEPRO_OPC_SB, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
|
{ { 0, }, { 8, 17 }, { 0, }, { 0, }, { 15, 36 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfe000000000000ULL,
|
0xfbfe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5153... |
Line 5191... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seq", TILEPRO_OPC_SEQ, 0xf, 3, TREG_ZERO, 1,
|
{ "seq", TILEPRO_OPC_SEQ, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 5172... |
Line 5210... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seq.sn", TILEPRO_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1,
|
{ "seq.sn", TILEPRO_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5191... |
Line 5229... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqb", TILEPRO_OPC_SEQB, 0x3, 3, TREG_ZERO, 1,
|
{ "seqb", TILEPRO_OPC_SEQB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5210... |
Line 5248... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqb.sn", TILEPRO_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1,
|
{ "seqb.sn", TILEPRO_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5229... |
Line 5267... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqh", TILEPRO_OPC_SEQH, 0x3, 3, TREG_ZERO, 1,
|
{ "seqh", TILEPRO_OPC_SEQH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5248... |
Line 5286... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqh.sn", TILEPRO_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1,
|
{ "seqh.sn", TILEPRO_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5267... |
Line 5305... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqi", TILEPRO_OPC_SEQI, 0xf, 3, TREG_ZERO, 1,
|
{ "seqi", TILEPRO_OPC_SEQI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x8000000078000000ULL,
|
0x8000000078000000ULL,
|
| Line 5286... |
Line 5324... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqi.sn", TILEPRO_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1,
|
{ "seqi.sn", TILEPRO_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5305... |
Line 5343... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqib", TILEPRO_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1,
|
{ "seqib", TILEPRO_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5324... |
Line 5362... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqib.sn", TILEPRO_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1,
|
{ "seqib.sn", TILEPRO_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5343... |
Line 5381... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqih", TILEPRO_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1,
|
{ "seqih", TILEPRO_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5362... |
Line 5400... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "seqih.sn", TILEPRO_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "seqih.sn", TILEPRO_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5381... |
Line 5419... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sh", TILEPRO_OPC_SH, 0x12, 2, TREG_ZERO, 1,
|
{ "sh", TILEPRO_OPC_SH, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
|
{ { 0, }, { 8, 17 }, { 0, }, { 0, }, { 15, 36 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfe000000000000ULL,
|
0xfbfe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5419... |
Line 5457... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl", TILEPRO_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
|
{ "shl", TILEPRO_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 5438... |
Line 5476... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shl.sn", TILEPRO_OPC_SHL_SN, 0x3, 3, TREG_SN, 1,
|
{ "shl.sn", TILEPRO_OPC_SHL_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5457... |
Line 5495... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlb", TILEPRO_OPC_SHLB, 0x3, 3, TREG_ZERO, 1,
|
{ "shlb", TILEPRO_OPC_SHLB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5476... |
Line 5514... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlb.sn", TILEPRO_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1,
|
{ "shlb.sn", TILEPRO_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5495... |
Line 5533... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlh", TILEPRO_OPC_SHLH, 0x3, 3, TREG_ZERO, 1,
|
{ "shlh", TILEPRO_OPC_SHLH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5514... |
Line 5552... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlh.sn", TILEPRO_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1,
|
{ "shlh.sn", TILEPRO_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5533... |
Line 5571... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shli", TILEPRO_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
|
{ "shli", TILEPRO_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0x80000000780e0000ULL,
|
0x80000000780e0000ULL,
|
| Line 5552... |
Line 5590... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shli.sn", TILEPRO_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1,
|
{ "shli.sn", TILEPRO_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5571... |
Line 5609... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlib", TILEPRO_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1,
|
{ "shlib", TILEPRO_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5590... |
Line 5628... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlib.sn", TILEPRO_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1,
|
{ "shlib.sn", TILEPRO_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5609... |
Line 5647... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlih", TILEPRO_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1,
|
{ "shlih", TILEPRO_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5628... |
Line 5666... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shlih.sn", TILEPRO_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "shlih.sn", TILEPRO_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5647... |
Line 5685... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shr", TILEPRO_OPC_SHR, 0xf, 3, TREG_ZERO, 1,
|
{ "shr", TILEPRO_OPC_SHR, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 5666... |
Line 5704... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shr.sn", TILEPRO_OPC_SHR_SN, 0x3, 3, TREG_SN, 1,
|
{ "shr.sn", TILEPRO_OPC_SHR_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5685... |
Line 5723... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrb", TILEPRO_OPC_SHRB, 0x3, 3, TREG_ZERO, 1,
|
{ "shrb", TILEPRO_OPC_SHRB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5704... |
Line 5742... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrb.sn", TILEPRO_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1,
|
{ "shrb.sn", TILEPRO_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5723... |
Line 5761... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrh", TILEPRO_OPC_SHRH, 0x3, 3, TREG_ZERO, 1,
|
{ "shrh", TILEPRO_OPC_SHRH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5742... |
Line 5780... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrh.sn", TILEPRO_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1,
|
{ "shrh.sn", TILEPRO_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5761... |
Line 5799... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shri", TILEPRO_OPC_SHRI, 0xf, 3, TREG_ZERO, 1,
|
{ "shri", TILEPRO_OPC_SHRI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0x80000000780e0000ULL,
|
0x80000000780e0000ULL,
|
| Line 5780... |
Line 5818... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shri.sn", TILEPRO_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1,
|
{ "shri.sn", TILEPRO_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5799... |
Line 5837... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrib", TILEPRO_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1,
|
{ "shrib", TILEPRO_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5818... |
Line 5856... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrib.sn", TILEPRO_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1,
|
{ "shrib.sn", TILEPRO_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5837... |
Line 5875... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrih", TILEPRO_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1,
|
{ "shrih", TILEPRO_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5856... |
Line 5894... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "shrih.sn", TILEPRO_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "shrih.sn", TILEPRO_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5875... |
Line 5913... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slt", TILEPRO_OPC_SLT, 0xf, 3, TREG_ZERO, 1,
|
{ "slt", TILEPRO_OPC_SLT, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 5894... |
Line 5932... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slt.sn", TILEPRO_OPC_SLT_SN, 0x3, 3, TREG_SN, 1,
|
{ "slt.sn", TILEPRO_OPC_SLT_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5913... |
Line 5951... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slt_u", TILEPRO_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1,
|
{ "slt_u", TILEPRO_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 5932... |
Line 5970... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slt_u.sn", TILEPRO_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "slt_u.sn", TILEPRO_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5951... |
Line 5989... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltb", TILEPRO_OPC_SLTB, 0x3, 3, TREG_ZERO, 1,
|
{ "sltb", TILEPRO_OPC_SLTB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5970... |
Line 6008... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltb.sn", TILEPRO_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1,
|
{ "sltb.sn", TILEPRO_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 5989... |
Line 6027... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltb_u", TILEPRO_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1,
|
{ "sltb_u", TILEPRO_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6008... |
Line 6046... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltb_u.sn", TILEPRO_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "sltb_u.sn", TILEPRO_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6027... |
Line 6065... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slte", TILEPRO_OPC_SLTE, 0xf, 3, TREG_ZERO, 1,
|
{ "slte", TILEPRO_OPC_SLTE, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 6046... |
Line 6084... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slte.sn", TILEPRO_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1,
|
{ "slte.sn", TILEPRO_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6065... |
Line 6103... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slte_u", TILEPRO_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1,
|
{ "slte_u", TILEPRO_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 6084... |
Line 6122... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slte_u.sn", TILEPRO_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "slte_u.sn", TILEPRO_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6103... |
Line 6141... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteb", TILEPRO_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1,
|
{ "slteb", TILEPRO_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6122... |
Line 6160... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteb.sn", TILEPRO_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1,
|
{ "slteb.sn", TILEPRO_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6141... |
Line 6179... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteb_u", TILEPRO_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1,
|
{ "slteb_u", TILEPRO_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6160... |
Line 6198... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteb_u.sn", TILEPRO_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "slteb_u.sn", TILEPRO_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6179... |
Line 6217... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteh", TILEPRO_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1,
|
{ "slteh", TILEPRO_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6198... |
Line 6236... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteh.sn", TILEPRO_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1,
|
{ "slteh.sn", TILEPRO_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6217... |
Line 6255... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteh_u", TILEPRO_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1,
|
{ "slteh_u", TILEPRO_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6236... |
Line 6274... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slteh_u.sn", TILEPRO_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "slteh_u.sn", TILEPRO_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6255... |
Line 6293... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slth", TILEPRO_OPC_SLTH, 0x3, 3, TREG_ZERO, 1,
|
{ "slth", TILEPRO_OPC_SLTH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6274... |
Line 6312... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slth.sn", TILEPRO_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1,
|
{ "slth.sn", TILEPRO_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6293... |
Line 6331... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slth_u", TILEPRO_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1,
|
{ "slth_u", TILEPRO_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6312... |
Line 6350... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slth_u.sn", TILEPRO_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "slth_u.sn", TILEPRO_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6331... |
Line 6369... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slti", TILEPRO_OPC_SLTI, 0xf, 3, TREG_ZERO, 1,
|
{ "slti", TILEPRO_OPC_SLTI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x8000000078000000ULL,
|
0x8000000078000000ULL,
|
| Line 6350... |
Line 6388... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slti.sn", TILEPRO_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1,
|
{ "slti.sn", TILEPRO_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6369... |
Line 6407... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slti_u", TILEPRO_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1,
|
{ "slti_u", TILEPRO_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0x8000000078000000ULL,
|
0x8000000078000000ULL,
|
| Line 6388... |
Line 6426... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "slti_u.sn", TILEPRO_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "slti_u.sn", TILEPRO_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6407... |
Line 6445... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltib", TILEPRO_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1,
|
{ "sltib", TILEPRO_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6426... |
Line 6464... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltib.sn", TILEPRO_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1,
|
{ "sltib.sn", TILEPRO_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6445... |
Line 6483... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltib_u", TILEPRO_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1,
|
{ "sltib_u", TILEPRO_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6464... |
Line 6502... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltib_u.sn", TILEPRO_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "sltib_u.sn", TILEPRO_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6483... |
Line 6521... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltih", TILEPRO_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1,
|
{ "sltih", TILEPRO_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6502... |
Line 6540... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltih.sn", TILEPRO_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "sltih.sn", TILEPRO_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6521... |
Line 6559... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltih_u", TILEPRO_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1,
|
{ "sltih_u", TILEPRO_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6540... |
Line 6578... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sltih_u.sn", TILEPRO_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "sltih_u.sn", TILEPRO_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6559... |
Line 6597... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sne", TILEPRO_OPC_SNE, 0xf, 3, TREG_ZERO, 1,
|
{ "sne", TILEPRO_OPC_SNE, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 6578... |
Line 6616... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sne.sn", TILEPRO_OPC_SNE_SN, 0x3, 3, TREG_SN, 1,
|
{ "sne.sn", TILEPRO_OPC_SNE_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6597... |
Line 6635... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sneb", TILEPRO_OPC_SNEB, 0x3, 3, TREG_ZERO, 1,
|
{ "sneb", TILEPRO_OPC_SNEB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6616... |
Line 6654... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sneb.sn", TILEPRO_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1,
|
{ "sneb.sn", TILEPRO_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6635... |
Line 6673... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sneh", TILEPRO_OPC_SNEH, 0x3, 3, TREG_ZERO, 1,
|
{ "sneh", TILEPRO_OPC_SNEH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6654... |
Line 6692... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sneh.sn", TILEPRO_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1,
|
{ "sneh.sn", TILEPRO_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6673... |
Line 6711... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sra", TILEPRO_OPC_SRA, 0xf, 3, TREG_ZERO, 1,
|
{ "sra", TILEPRO_OPC_SRA, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 6692... |
Line 6730... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sra.sn", TILEPRO_OPC_SRA_SN, 0x3, 3, TREG_SN, 1,
|
{ "sra.sn", TILEPRO_OPC_SRA_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6711... |
Line 6749... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "srab", TILEPRO_OPC_SRAB, 0x3, 3, TREG_ZERO, 1,
|
{ "srab", TILEPRO_OPC_SRAB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6730... |
Line 6768... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "srab.sn", TILEPRO_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1,
|
{ "srab.sn", TILEPRO_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6749... |
Line 6787... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "srah", TILEPRO_OPC_SRAH, 0x3, 3, TREG_ZERO, 1,
|
{ "srah", TILEPRO_OPC_SRAH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6768... |
Line 6806... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "srah.sn", TILEPRO_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1,
|
{ "srah.sn", TILEPRO_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6787... |
Line 6825... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "srai", TILEPRO_OPC_SRAI, 0xf, 3, TREG_ZERO, 1,
|
{ "srai", TILEPRO_OPC_SRAI, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0x80000000780e0000ULL,
|
0x80000000780e0000ULL,
|
| Line 6806... |
Line 6844... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "srai.sn", TILEPRO_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1,
|
{ "srai.sn", TILEPRO_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6825... |
Line 6863... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sraib", TILEPRO_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1,
|
{ "sraib", TILEPRO_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6844... |
Line 6882... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sraib.sn", TILEPRO_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1,
|
{ "sraib.sn", TILEPRO_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6863... |
Line 6901... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sraih", TILEPRO_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1,
|
{ "sraih", TILEPRO_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6882... |
Line 6920... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sraih.sn", TILEPRO_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1,
|
{ "sraih.sn", TILEPRO_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 32 }, { 7, 8, 33 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffe0000ULL,
|
0x800000007ffe0000ULL,
|
0xffff000000000000ULL,
|
0xffff000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6901... |
Line 6939... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sub", TILEPRO_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
|
{ "sub", TILEPRO_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 6920... |
Line 6958... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sub.sn", TILEPRO_OPC_SUB_SN, 0x3, 3, TREG_SN, 1,
|
{ "sub.sn", TILEPRO_OPC_SUB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6939... |
Line 6977... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subb", TILEPRO_OPC_SUBB, 0x3, 3, TREG_ZERO, 1,
|
{ "subb", TILEPRO_OPC_SUBB, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6958... |
Line 6996... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subb.sn", TILEPRO_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1,
|
{ "subb.sn", TILEPRO_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6977... |
Line 7015... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subbs_u", TILEPRO_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1,
|
{ "subbs_u", TILEPRO_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 6996... |
Line 7034... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subbs_u.sn", TILEPRO_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1,
|
{ "subbs_u.sn", TILEPRO_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7015... |
Line 7053... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subh", TILEPRO_OPC_SUBH, 0x3, 3, TREG_ZERO, 1,
|
{ "subh", TILEPRO_OPC_SUBH, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7034... |
Line 7072... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subh.sn", TILEPRO_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1,
|
{ "subh.sn", TILEPRO_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7053... |
Line 7091... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subhs", TILEPRO_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1,
|
{ "subhs", TILEPRO_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7072... |
Line 7110... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subhs.sn", TILEPRO_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1,
|
{ "subhs.sn", TILEPRO_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7091... |
Line 7129... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subs", TILEPRO_OPC_SUBS, 0x3, 3, TREG_ZERO, 1,
|
{ "subs", TILEPRO_OPC_SUBS, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7110... |
Line 7148... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "subs.sn", TILEPRO_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1,
|
{ "subs.sn", TILEPRO_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7129... |
Line 7167... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "sw", TILEPRO_OPC_SW, 0x12, 2, TREG_ZERO, 1,
|
{ "sw", TILEPRO_OPC_SW, 0x12, 2, TREG_ZERO, 1,
|
{ { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
|
{ { 0, }, { 8, 17 }, { 0, }, { 0, }, { 15, 36 } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfe000000000000ULL,
|
0xfbfe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7243... |
Line 7281... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb0", TILEPRO_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb0", TILEPRO_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
|
{ { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 7262... |
Line 7300... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb0.sn", TILEPRO_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1,
|
{ "tblidxb0.sn", TILEPRO_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1,
|
{ { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 7281... |
Line 7319... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb1", TILEPRO_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb1", TILEPRO_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
|
{ { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 7300... |
Line 7338... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb1.sn", TILEPRO_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1,
|
{ "tblidxb1.sn", TILEPRO_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1,
|
{ { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 7319... |
Line 7357... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb2", TILEPRO_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb2", TILEPRO_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
|
{ { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 7338... |
Line 7376... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb2.sn", TILEPRO_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1,
|
{ "tblidxb2.sn", TILEPRO_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1,
|
{ { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 7357... |
Line 7395... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb3", TILEPRO_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
|
{ "tblidxb3", TILEPRO_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
|
{ { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0x80000000780ff000ULL,
|
0x80000000780ff000ULL,
|
| Line 7376... |
Line 7414... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tblidxb3.sn", TILEPRO_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1,
|
{ "tblidxb3.sn", TILEPRO_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1,
|
{ { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
{ { 21, 10 }, { 0, }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffff000ULL,
|
0x800000007ffff000ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
0ULL,
|
| Line 7395... |
Line 7433... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tns", TILEPRO_OPC_TNS, 0x2, 2, TREG_ZERO, 1,
|
{ "tns", TILEPRO_OPC_TNS, 0x2, 2, TREG_ZERO, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7414... |
Line 7452... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "tns.sn", TILEPRO_OPC_TNS_SN, 0x2, 2, TREG_SN, 1,
|
{ "tns.sn", TILEPRO_OPC_TNS_SN, 0x2, 2, TREG_SN, 1,
|
{ { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 7, 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfffff80000000000ULL,
|
0xfffff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7433... |
Line 7471... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "wh64", TILEPRO_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
|
{ "wh64", TILEPRO_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
|
{ { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
|
{ { 0, }, { 8 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0ULL,
|
0ULL,
|
0xfbfff80000000000ULL,
|
0xfbfff80000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7452... |
Line 7490... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "xor", TILEPRO_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
|
{ "xor", TILEPRO_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0x80000000780c0000ULL,
|
0x80000000780c0000ULL,
|
| Line 7471... |
Line 7509... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "xor.sn", TILEPRO_OPC_XOR_SN, 0x3, 3, TREG_SN, 1,
|
{ "xor.sn", TILEPRO_OPC_XOR_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 16 }, { 7, 8, 17 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ffc0000ULL,
|
0x800000007ffc0000ULL,
|
0xfffe000000000000ULL,
|
0xfffe000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7490... |
Line 7528... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "xori", TILEPRO_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
|
{ "xori", TILEPRO_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7509... |
Line 7547... |
-1ULL
|
-1ULL
|
}
|
}
|
#endif
|
#endif
|
},
|
},
|
{ "xori.sn", TILEPRO_OPC_XORI_SN, 0x3, 3, TREG_SN, 1,
|
{ "xori.sn", TILEPRO_OPC_XORI_SN, 0x3, 3, TREG_SN, 1,
|
{ { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
|
{ { 9, 10, 0 }, { 7, 8, 1 }, { 0, }, { 0, }, { 0, } },
|
#ifndef DISASM_ONLY
|
#ifndef DISASM_ONLY
|
{
|
{
|
0x800000007ff00000ULL,
|
0x800000007ff00000ULL,
|
0xfff8000000000000ULL,
|
0xfff8000000000000ULL,
|
0ULL,
|
0ULL,
|
| Line 7933... |
Line 7971... |
TILEPRO_OPC_TBLIDXB2_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_TBLIDXB2_SN, TILEPRO_OPC_NONE,
|
BITFIELD(16, 1) /* index 1150 */,
|
BITFIELD(16, 1) /* index 1150 */,
|
TILEPRO_OPC_TBLIDXB3_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_TBLIDXB3_SN, TILEPRO_OPC_NONE,
|
};
|
};
|
|
|
static const unsigned short decode_X1_fsm[1540] =
|
static const unsigned short decode_X1_fsm[1580] =
|
{
|
{
|
BITFIELD(54, 9) /* index 0 */,
|
BITFIELD(54, 9) /* index 0 */,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
| Line 7977... |
Line 8015... |
CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
|
CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
|
CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932),
|
CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932),
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
CHILD(941), CHILD(950), CHILD(974), CHILD(983), TILEPRO_OPC_NONE,
|
CHILD(961), CHILD(970), CHILD(994), CHILD(1003), TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(992),
|
TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(1032),
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1334),
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1374),
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
| Line 8221... |
Line 8259... |
BITFIELD(51, 3) /* index 923 */,
|
BITFIELD(51, 3) /* index 923 */,
|
TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH, TILEPRO_OPC_SLTIH_U,
|
TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH, TILEPRO_OPC_SLTIH_U,
|
TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_XORI, TILEPRO_OPC_LBADD,
|
TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_XORI, TILEPRO_OPC_LBADD,
|
TILEPRO_OPC_LBADD_U,
|
TILEPRO_OPC_LBADD_U,
|
BITFIELD(51, 3) /* index 932 */,
|
BITFIELD(51, 3) /* index 932 */,
|
TILEPRO_OPC_LHADD, TILEPRO_OPC_LHADD_U, TILEPRO_OPC_LWADD,
|
TILEPRO_OPC_LHADD, TILEPRO_OPC_LHADD_U, CHILD(941), TILEPRO_OPC_LWADD_NA,
|
TILEPRO_OPC_LWADD_NA, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD,
|
TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD, TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE,
|
BITFIELD(43, 2) /* index 941 */,
|
BITFIELD(51, 3) /* index 941 */,
|
CHILD(946), TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD,
|
|
BITFIELD(45, 2) /* index 946 */,
|
|
CHILD(951), TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD,
|
|
BITFIELD(47, 2) /* index 951 */,
|
|
CHILD(956), TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD,
|
|
BITFIELD(49, 2) /* index 956 */,
|
|
TILEPRO_OPC_LW_TLS, TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD, TILEPRO_OPC_LWADD,
|
|
BITFIELD(51, 3) /* index 961 */,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN,
|
TILEPRO_OPC_ADDI_SN, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_MAXIB_U_SN,
|
TILEPRO_OPC_ADDI_SN, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_MAXIB_U_SN,
|
TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MFSPR,
|
TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MFSPR,
|
BITFIELD(51, 3) /* index 950 */,
|
BITFIELD(51, 3) /* index 970 */,
|
TILEPRO_OPC_MINIB_U_SN, TILEPRO_OPC_MINIH_SN, TILEPRO_OPC_MTSPR, CHILD(959),
|
TILEPRO_OPC_MINIB_U_SN, TILEPRO_OPC_MINIH_SN, TILEPRO_OPC_MTSPR, CHILD(979),
|
TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN,
|
TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN,
|
TILEPRO_OPC_SLTIB_SN,
|
TILEPRO_OPC_SLTIB_SN,
|
BITFIELD(37, 2) /* index 959 */,
|
BITFIELD(37, 2) /* index 979 */,
|
TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(964),
|
TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(984),
|
BITFIELD(39, 2) /* index 964 */,
|
BITFIELD(39, 2) /* index 984 */,
|
TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(969),
|
TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(989),
|
BITFIELD(41, 2) /* index 969 */,
|
BITFIELD(41, 2) /* index 989 */,
|
TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN,
|
TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN,
|
TILEPRO_OPC_MOVEI_SN,
|
TILEPRO_OPC_MOVEI_SN,
|
BITFIELD(51, 3) /* index 974 */,
|
BITFIELD(51, 3) /* index 994 */,
|
TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN, TILEPRO_OPC_SLTIH_U_SN,
|
TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN, TILEPRO_OPC_SLTIH_U_SN,
|
TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_XORI_SN,
|
TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_XORI_SN,
|
TILEPRO_OPC_LBADD_SN, TILEPRO_OPC_LBADD_U_SN,
|
TILEPRO_OPC_LBADD_SN, TILEPRO_OPC_LBADD_U_SN,
|
BITFIELD(51, 3) /* index 983 */,
|
BITFIELD(51, 3) /* index 1003 */,
|
TILEPRO_OPC_LHADD_SN, TILEPRO_OPC_LHADD_U_SN, TILEPRO_OPC_LWADD_SN,
|
TILEPRO_OPC_LHADD_SN, TILEPRO_OPC_LHADD_U_SN, CHILD(1012),
|
TILEPRO_OPC_LWADD_NA_SN, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD,
|
TILEPRO_OPC_LWADD_NA_SN, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD,
|
TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE,
|
BITFIELD(46, 7) /* index 992 */,
|
BITFIELD(43, 2) /* index 1012 */,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
CHILD(1017), TILEPRO_OPC_LWADD_SN, TILEPRO_OPC_LWADD_SN,
|
CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1124),
|
TILEPRO_OPC_LWADD_SN,
|
CHILD(1124), CHILD(1124), CHILD(1124), CHILD(1127), CHILD(1127),
|
BITFIELD(45, 2) /* index 1017 */,
|
CHILD(1127), CHILD(1127), CHILD(1130), CHILD(1130), CHILD(1130),
|
CHILD(1022), TILEPRO_OPC_LWADD_SN, TILEPRO_OPC_LWADD_SN,
|
CHILD(1130), CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1133),
|
TILEPRO_OPC_LWADD_SN,
|
CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1139),
|
BITFIELD(47, 2) /* index 1022 */,
|
CHILD(1139), CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142),
|
CHILD(1027), TILEPRO_OPC_LWADD_SN, TILEPRO_OPC_LWADD_SN,
|
CHILD(1142), CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145),
|
TILEPRO_OPC_LWADD_SN,
|
CHILD(1145), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148),
|
BITFIELD(49, 2) /* index 1027 */,
|
CHILD(1151), CHILD(1242), CHILD(1290), CHILD(1323), TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LW_TLS_SN, TILEPRO_OPC_LWADD_SN, TILEPRO_OPC_LWADD_SN,
|
|
TILEPRO_OPC_LWADD_SN,
|
|
BITFIELD(46, 7) /* index 1032 */,
|
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
|
CHILD(1161), CHILD(1161), CHILD(1161), CHILD(1161), CHILD(1164),
|
|
CHILD(1164), CHILD(1164), CHILD(1164), CHILD(1167), CHILD(1167),
|
|
CHILD(1167), CHILD(1167), CHILD(1170), CHILD(1170), CHILD(1170),
|
|
CHILD(1170), CHILD(1173), CHILD(1173), CHILD(1173), CHILD(1173),
|
|
CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1179),
|
|
CHILD(1179), CHILD(1179), CHILD(1179), CHILD(1182), CHILD(1182),
|
|
CHILD(1182), CHILD(1182), CHILD(1185), CHILD(1185), CHILD(1185),
|
|
CHILD(1185), CHILD(1188), CHILD(1188), CHILD(1188), CHILD(1188),
|
|
CHILD(1191), CHILD(1282), CHILD(1330), CHILD(1363), TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
| Line 8278... |
Line 8335... |
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1121 */,
|
BITFIELD(53, 1) /* index 1161 */,
|
TILEPRO_OPC_RLI, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_RLI, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1124 */,
|
BITFIELD(53, 1) /* index 1164 */,
|
TILEPRO_OPC_SHLIB, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHLIB, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1127 */,
|
BITFIELD(53, 1) /* index 1167 */,
|
TILEPRO_OPC_SHLIH, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHLIH, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1130 */,
|
BITFIELD(53, 1) /* index 1170 */,
|
TILEPRO_OPC_SHLI, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHLI, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1133 */,
|
BITFIELD(53, 1) /* index 1173 */,
|
TILEPRO_OPC_SHRIB, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHRIB, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1136 */,
|
BITFIELD(53, 1) /* index 1176 */,
|
TILEPRO_OPC_SHRIH, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHRIH, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1139 */,
|
BITFIELD(53, 1) /* index 1179 */,
|
TILEPRO_OPC_SHRI, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHRI, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1142 */,
|
BITFIELD(53, 1) /* index 1182 */,
|
TILEPRO_OPC_SRAIB, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SRAIB, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1145 */,
|
BITFIELD(53, 1) /* index 1185 */,
|
TILEPRO_OPC_SRAIH, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SRAIH, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1148 */,
|
BITFIELD(53, 1) /* index 1188 */,
|
TILEPRO_OPC_SRAI, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SRAI, TILEPRO_OPC_NONE,
|
BITFIELD(43, 3) /* index 1151 */,
|
BITFIELD(43, 3) /* index 1191 */,
|
TILEPRO_OPC_NONE, CHILD(1160), CHILD(1163), CHILD(1166), CHILD(1169),
|
TILEPRO_OPC_NONE, CHILD(1200), CHILD(1203), CHILD(1206), CHILD(1209),
|
CHILD(1172), CHILD(1175), CHILD(1178),
|
CHILD(1212), CHILD(1215), CHILD(1218),
|
BITFIELD(53, 1) /* index 1160 */,
|
BITFIELD(53, 1) /* index 1200 */,
|
TILEPRO_OPC_DRAIN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_DRAIN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1163 */,
|
BITFIELD(53, 1) /* index 1203 */,
|
TILEPRO_OPC_DTLBPR, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_DTLBPR, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1166 */,
|
BITFIELD(53, 1) /* index 1206 */,
|
TILEPRO_OPC_FINV, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_FINV, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1169 */,
|
BITFIELD(53, 1) /* index 1209 */,
|
TILEPRO_OPC_FLUSH, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_FLUSH, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1172 */,
|
BITFIELD(53, 1) /* index 1212 */,
|
TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1175 */,
|
BITFIELD(53, 1) /* index 1215 */,
|
TILEPRO_OPC_ICOH, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_ICOH, TILEPRO_OPC_NONE,
|
BITFIELD(31, 2) /* index 1178 */,
|
BITFIELD(31, 2) /* index 1218 */,
|
CHILD(1183), CHILD(1211), CHILD(1239), CHILD(1239),
|
CHILD(1223), CHILD(1251), CHILD(1279), CHILD(1279),
|
BITFIELD(53, 1) /* index 1183 */,
|
BITFIELD(53, 1) /* index 1223 */,
|
CHILD(1186), TILEPRO_OPC_NONE,
|
CHILD(1226), TILEPRO_OPC_NONE,
|
BITFIELD(33, 2) /* index 1186 */,
|
BITFIELD(33, 2) /* index 1226 */,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1191),
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1231),
|
BITFIELD(35, 2) /* index 1191 */,
|
BITFIELD(35, 2) /* index 1231 */,
|
TILEPRO_OPC_ILL, CHILD(1196), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, CHILD(1236), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
BITFIELD(37, 2) /* index 1196 */,
|
BITFIELD(37, 2) /* index 1236 */,
|
TILEPRO_OPC_ILL, CHILD(1201), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, CHILD(1241), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
BITFIELD(39, 2) /* index 1201 */,
|
BITFIELD(39, 2) /* index 1241 */,
|
TILEPRO_OPC_ILL, CHILD(1206), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, CHILD(1246), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
BITFIELD(41, 2) /* index 1206 */,
|
BITFIELD(41, 2) /* index 1246 */,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_BPT, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_BPT, TILEPRO_OPC_ILL,
|
BITFIELD(53, 1) /* index 1211 */,
|
BITFIELD(53, 1) /* index 1251 */,
|
CHILD(1214), TILEPRO_OPC_NONE,
|
CHILD(1254), TILEPRO_OPC_NONE,
|
BITFIELD(33, 2) /* index 1214 */,
|
BITFIELD(33, 2) /* index 1254 */,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1219),
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1259),
|
BITFIELD(35, 2) /* index 1219 */,
|
BITFIELD(35, 2) /* index 1259 */,
|
TILEPRO_OPC_ILL, CHILD(1224), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, CHILD(1264), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
BITFIELD(37, 2) /* index 1224 */,
|
BITFIELD(37, 2) /* index 1264 */,
|
TILEPRO_OPC_ILL, CHILD(1229), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, CHILD(1269), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
BITFIELD(39, 2) /* index 1229 */,
|
BITFIELD(39, 2) /* index 1269 */,
|
TILEPRO_OPC_ILL, CHILD(1234), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, CHILD(1274), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
|
BITFIELD(41, 2) /* index 1234 */,
|
BITFIELD(41, 2) /* index 1274 */,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_RAISE, TILEPRO_OPC_ILL,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_RAISE, TILEPRO_OPC_ILL,
|
BITFIELD(53, 1) /* index 1239 */,
|
BITFIELD(53, 1) /* index 1279 */,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_ILL, TILEPRO_OPC_NONE,
|
BITFIELD(43, 3) /* index 1242 */,
|
BITFIELD(43, 3) /* index 1282 */,
|
CHILD(1251), CHILD(1254), CHILD(1257), CHILD(1275), CHILD(1278),
|
CHILD(1291), CHILD(1294), CHILD(1297), CHILD(1315), CHILD(1318),
|
CHILD(1281), CHILD(1284), CHILD(1287),
|
CHILD(1321), CHILD(1324), CHILD(1327),
|
BITFIELD(53, 1) /* index 1251 */,
|
BITFIELD(53, 1) /* index 1291 */,
|
TILEPRO_OPC_INV, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_INV, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1254 */,
|
BITFIELD(53, 1) /* index 1294 */,
|
TILEPRO_OPC_IRET, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_IRET, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1257 */,
|
BITFIELD(53, 1) /* index 1297 */,
|
CHILD(1260), TILEPRO_OPC_NONE,
|
CHILD(1300), TILEPRO_OPC_NONE,
|
BITFIELD(31, 2) /* index 1260 */,
|
BITFIELD(31, 2) /* index 1300 */,
|
TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1265),
|
TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1305),
|
BITFIELD(33, 2) /* index 1265 */,
|
BITFIELD(33, 2) /* index 1305 */,
|
TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1270),
|
TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1310),
|
BITFIELD(35, 2) /* index 1270 */,
|
BITFIELD(35, 2) /* index 1310 */,
|
TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH,
|
TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH,
|
BITFIELD(53, 1) /* index 1275 */,
|
BITFIELD(53, 1) /* index 1315 */,
|
TILEPRO_OPC_LB_U, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LB_U, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1278 */,
|
BITFIELD(53, 1) /* index 1318 */,
|
TILEPRO_OPC_LH, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LH, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1281 */,
|
BITFIELD(53, 1) /* index 1321 */,
|
TILEPRO_OPC_LH_U, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LH_U, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1284 */,
|
BITFIELD(53, 1) /* index 1324 */,
|
TILEPRO_OPC_LW, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LW, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1287 */,
|
BITFIELD(53, 1) /* index 1327 */,
|
TILEPRO_OPC_MF, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_MF, TILEPRO_OPC_NONE,
|
BITFIELD(43, 3) /* index 1290 */,
|
BITFIELD(43, 3) /* index 1330 */,
|
CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311),
|
CHILD(1339), CHILD(1342), CHILD(1345), CHILD(1348), CHILD(1351),
|
CHILD(1314), CHILD(1317), CHILD(1320),
|
CHILD(1354), CHILD(1357), CHILD(1360),
|
BITFIELD(53, 1) /* index 1299 */,
|
BITFIELD(53, 1) /* index 1339 */,
|
TILEPRO_OPC_NAP, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NAP, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1302 */,
|
BITFIELD(53, 1) /* index 1342 */,
|
TILEPRO_OPC_NOP, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NOP, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1305 */,
|
BITFIELD(53, 1) /* index 1345 */,
|
TILEPRO_OPC_SWINT0, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SWINT0, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1308 */,
|
BITFIELD(53, 1) /* index 1348 */,
|
TILEPRO_OPC_SWINT1, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SWINT1, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1311 */,
|
BITFIELD(53, 1) /* index 1351 */,
|
TILEPRO_OPC_SWINT2, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SWINT2, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1314 */,
|
BITFIELD(53, 1) /* index 1354 */,
|
TILEPRO_OPC_SWINT3, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SWINT3, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1317 */,
|
BITFIELD(53, 1) /* index 1357 */,
|
TILEPRO_OPC_TNS, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_TNS, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1320 */,
|
BITFIELD(53, 1) /* index 1360 */,
|
TILEPRO_OPC_WH64, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_WH64, TILEPRO_OPC_NONE,
|
BITFIELD(43, 2) /* index 1323 */,
|
BITFIELD(43, 2) /* index 1363 */,
|
CHILD(1328), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
CHILD(1368), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
BITFIELD(45, 1) /* index 1328 */,
|
BITFIELD(45, 1) /* index 1368 */,
|
CHILD(1331), TILEPRO_OPC_NONE,
|
CHILD(1371), TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1331 */,
|
BITFIELD(53, 1) /* index 1371 */,
|
TILEPRO_OPC_LW_NA, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LW_NA, TILEPRO_OPC_NONE,
|
BITFIELD(46, 7) /* index 1334 */,
|
BITFIELD(46, 7) /* index 1374 */,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1466),
|
CHILD(1503), CHILD(1503), CHILD(1503), CHILD(1503), CHILD(1506),
|
CHILD(1466), CHILD(1466), CHILD(1466), CHILD(1469), CHILD(1469),
|
CHILD(1506), CHILD(1506), CHILD(1506), CHILD(1509), CHILD(1509),
|
CHILD(1469), CHILD(1469), CHILD(1472), CHILD(1472), CHILD(1472),
|
CHILD(1509), CHILD(1509), CHILD(1512), CHILD(1512), CHILD(1512),
|
CHILD(1472), CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1475),
|
CHILD(1512), CHILD(1515), CHILD(1515), CHILD(1515), CHILD(1515),
|
CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1481),
|
CHILD(1518), CHILD(1518), CHILD(1518), CHILD(1518), CHILD(1521),
|
CHILD(1481), CHILD(1481), CHILD(1481), CHILD(1484), CHILD(1484),
|
CHILD(1521), CHILD(1521), CHILD(1521), CHILD(1524), CHILD(1524),
|
CHILD(1484), CHILD(1484), CHILD(1487), CHILD(1487), CHILD(1487),
|
CHILD(1524), CHILD(1524), CHILD(1527), CHILD(1527), CHILD(1527),
|
CHILD(1487), CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1490),
|
CHILD(1527), CHILD(1530), CHILD(1530), CHILD(1530), CHILD(1530),
|
CHILD(1151), CHILD(1493), CHILD(1517), CHILD(1529), TILEPRO_OPC_NONE,
|
CHILD(1191), CHILD(1533), CHILD(1557), CHILD(1569), TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
| Line 8422... |
Line 8479... |
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1463 */,
|
BITFIELD(53, 1) /* index 1503 */,
|
TILEPRO_OPC_RLI_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_RLI_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1466 */,
|
BITFIELD(53, 1) /* index 1506 */,
|
TILEPRO_OPC_SHLIB_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHLIB_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1469 */,
|
BITFIELD(53, 1) /* index 1509 */,
|
TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1472 */,
|
BITFIELD(53, 1) /* index 1512 */,
|
TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1475 */,
|
BITFIELD(53, 1) /* index 1515 */,
|
TILEPRO_OPC_SHRIB_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHRIB_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1478 */,
|
BITFIELD(53, 1) /* index 1518 */,
|
TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1481 */,
|
BITFIELD(53, 1) /* index 1521 */,
|
TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1484 */,
|
BITFIELD(53, 1) /* index 1524 */,
|
TILEPRO_OPC_SRAIB_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SRAIB_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1487 */,
|
BITFIELD(53, 1) /* index 1527 */,
|
TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1490 */,
|
BITFIELD(53, 1) /* index 1530 */,
|
TILEPRO_OPC_SRAI_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_SRAI_SN, TILEPRO_OPC_NONE,
|
BITFIELD(43, 3) /* index 1493 */,
|
BITFIELD(43, 3) /* index 1533 */,
|
CHILD(1251), CHILD(1254), CHILD(1502), CHILD(1505), CHILD(1508),
|
CHILD(1291), CHILD(1294), CHILD(1542), CHILD(1545), CHILD(1548),
|
CHILD(1511), CHILD(1514), CHILD(1287),
|
CHILD(1551), CHILD(1554), CHILD(1327),
|
BITFIELD(53, 1) /* index 1502 */,
|
BITFIELD(53, 1) /* index 1542 */,
|
TILEPRO_OPC_LB_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LB_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1505 */,
|
BITFIELD(53, 1) /* index 1545 */,
|
TILEPRO_OPC_LB_U_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LB_U_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1508 */,
|
BITFIELD(53, 1) /* index 1548 */,
|
TILEPRO_OPC_LH_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LH_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1511 */,
|
BITFIELD(53, 1) /* index 1551 */,
|
TILEPRO_OPC_LH_U_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LH_U_SN, TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1514 */,
|
BITFIELD(53, 1) /* index 1554 */,
|
TILEPRO_OPC_LW_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LW_SN, TILEPRO_OPC_NONE,
|
BITFIELD(43, 3) /* index 1517 */,
|
BITFIELD(43, 3) /* index 1557 */,
|
CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311),
|
CHILD(1339), CHILD(1342), CHILD(1345), CHILD(1348), CHILD(1351),
|
CHILD(1314), CHILD(1526), CHILD(1320),
|
CHILD(1354), CHILD(1566), CHILD(1360),
|
BITFIELD(53, 1) /* index 1526 */,
|
BITFIELD(53, 1) /* index 1566 */,
|
TILEPRO_OPC_TNS_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_TNS_SN, TILEPRO_OPC_NONE,
|
BITFIELD(43, 2) /* index 1529 */,
|
BITFIELD(43, 2) /* index 1569 */,
|
CHILD(1534), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
CHILD(1574), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
|
BITFIELD(45, 1) /* index 1534 */,
|
BITFIELD(45, 1) /* index 1574 */,
|
CHILD(1537), TILEPRO_OPC_NONE,
|
CHILD(1577), TILEPRO_OPC_NONE,
|
BITFIELD(53, 1) /* index 1537 */,
|
BITFIELD(53, 1) /* index 1577 */,
|
TILEPRO_OPC_LW_NA_SN, TILEPRO_OPC_NONE,
|
TILEPRO_OPC_LW_NA_SN, TILEPRO_OPC_NONE,
|
};
|
};
|
|
|
static const unsigned short decode_Y0_fsm[168] =
|
static const unsigned short decode_Y0_fsm[168] =
|
{
|
{
|
| Line 9356... |
Line 9413... |
create_JOffLong_X1, get_JOffLong_X1
|
create_JOffLong_X1, get_JOffLong_X1
|
},
|
},
|
{
|
{
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 0, 1, 0, 0,
|
6, 0, 0, 1, 0, 0,
|
create_Dest_X0, get_Dest_X0
|
create_Dest_X1, get_Dest_X1
|
},
|
},
|
{
|
{
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 1, 0, 0, 0,
|
6, 0, 1, 0, 0, 0,
|
create_SrcA_X0, get_SrcA_X0
|
create_SrcA_X1, get_SrcA_X1
|
},
|
},
|
{
|
{
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 0, 1, 0, 0,
|
6, 0, 0, 1, 0, 0,
|
create_Dest_X1, get_Dest_X1
|
create_Dest_X0, get_Dest_X0
|
},
|
},
|
{
|
{
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 1, 0, 0, 0,
|
6, 0, 1, 0, 0, 0,
|
create_SrcA_X1, get_SrcA_X1
|
create_SrcA_X0, get_SrcA_X0
|
},
|
},
|
{
|
{
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
|
6, 0, 0, 1, 0, 0,
|
6, 0, 0, 1, 0, 0,
|
create_Dest_Y0, get_Dest_Y0
|
create_Dest_Y0, get_Dest_Y0
|
