OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [taskmgr/] [taskmgr_const.s] - Diff between revs 306 and 309

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 306 Rev 309
Line 59... Line 59...
 
 
; I/O Write Qualification Register
; I/O Write Qualification Register
.DEFINE IO_WRITE_QUAL        WQL_Address
.DEFINE IO_WRITE_QUAL        WQL_Address
 
 
; External Interrupt Manager / Task Timer
; External Interrupt Manager / Task Timer
.DEFINE INT_MGR_IF           INT_Address ; Shared with the main
.DEFINE INT_MGR_IF           INT_Address
.DEFINE TASK_TIMER_PRD       INT_MGR_IF  + 0
.DEFINE TASK_TIMER_PRD       INT_MGR_IF  + 0
 
 
; Defines for the 8-bit interrupt manager
; Defines for the 8-bit interrupt manager
.DEFINE EXT_INT_MASK         INT_MGR_IF + 1
.DEFINE EXT_INT_MASK         INT_MGR_IF + 1
.DEFINE EXT_INT_PEND         INT_MGR_IF + 2
.DEFINE EXT_INT_PEND         INT_MGR_IF + 2
Line 130... Line 130...
.DEFINE FREE_SYSMEM_PTR      BOOT_BLOCK +  6
.DEFINE FREE_SYSMEM_PTR      BOOT_BLOCK +  6
.DEFINE TASK_PARAMS_PTR      BOOT_BLOCK +  8
.DEFINE TASK_PARAMS_PTR      BOOT_BLOCK +  8
.DEFINE TASK_PARAM_TABLE     BOOT_BLOCK +  10
.DEFINE TASK_PARAM_TABLE     BOOT_BLOCK +  10
 
 
.MACRO INSTANCE_TASK_POINTERS
.MACRO INSTANCE_TASK_POINTERS
 
 
.DW TaskMgr.Task_Stacks   ; ( + 4) First available RAM location for stack data
.DW TaskMgr.Task_Stacks   ; ( + 4) First available RAM location for stack data
.DW TaskMgr.Free_Mem      ; ( + 6) First available free RAM location in sysmem
.DW TaskMgr.Free_Mem      ; ( + 6) First available free RAM location in sysmem
.DW TASK_PARAM_TABLE      ; ( + 8) Start of task parameter table
.DW TASK_PARAM_TABLE      ; ( + 8) Start of task parameter table
.ENDM
.ENDM
 
 
Line 267... Line 266...
.ENDM
.ENDM
 
 
.MACRO RELOCATE_SP
.MACRO RELOCATE_SP
              STP  PSR_S   ; Affirmatively set PSR_S flag first
              STP  PSR_S   ; Affirmatively set PSR_S flag first
              RSP          ; Execute the RSP instruction
              RSP          ; Execute the RSP instruction
              CLP  PSR_S   ; Reset PSR_GP4 afterward
              CLP  PSR_S   ; Reset PSR_S afterward
.ENDM
.ENDM
 
 
; Task initialization, switching time, and init/exec macros
; Task initialization, switching time, and init/exec macros
.MACRO DISABLE_PREEMPTION_TIMER
.MACRO DISABLE_PREEMPTION_TIMER
              CLR  R0                     ; Make sure the PIT is disabled
              CLR  R0                     ; Make sure the PIT is disabled
Line 762... Line 761...
              LDI  R0, #EXT_INTERRUPT_EN_H; Re-enable the external interrupts
              LDI  R0, #EXT_INTERRUPT_EN_H; Re-enable the external interrupts
              STA  R0, EXT_INT16_MASK_H
              STA  R0, EXT_INT16_MASK_H
.ENDM
.ENDM
 
 
; Sets up an individual external interrupt macro. Note that these refer to
; Sets up an individual external interrupt macro. Note that these refer to
;  macros defined in ext_isr_config.s
;  macros defined in taskmgr_config.s
 
 
.MACRO PROCESS_EXT_ISR
.MACRO PROCESS_EXT_ISR
              SET_INT\@_FLAGS
              SET_INT\@_FLAGS
 
 
              TX0  R3                  ; When done with the flags, update the
              TX0  R3                  ; When done with the flags, update the

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.