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[/] [open_hitter/] [trunk/] [bench/] [vhdl/] [hitter_wrapper.vhd] - Diff between revs 2 and 3

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-- hitter_wrapper.vhd
--////////////////////////////////////////////////////////////////////
-- Synthesizable wrapper, exercise wrapper with NSEW buttons and LEDs to report on fpga dev board
--//                                                              ////
-- target env: Xilinx Virtex 6 / ML605
--// hitter_wrapper.vhd                                           ////
--
--//                                                              ////
-- <LGPL Required>
--// This file is part of the open_hitter opencores effort.       ////
-- <History from svn, link required>
--// <http://www.opencores.org/cores/open_hitter/>                ////
 
--//                                                              ////
 
--// Module Description:                                          ////
 
--// Simulation program (non-synthesizable)                       ////
 
--// Drives auto regression tests via NSEW button actions and     ////
 
--// NSEW LED reporting                                           ////
 
--// target env: ghdl <attrib required>                           ////
 
--//                                                              ////
 
--// To Do:                                                       ////
 
--//    #LOTS                                                     ////
 
--//                                                              ////
 
--// Author(s):                                                   ////
 
--// - Stephen Hawes                                              ////
 
--//                                                              ////
 
--////////////////////////////////////////////////////////////////////
 
--//                                                              ////
 
--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG           ////
 
--//                                                              ////
 
--// This source file may be used and distributed without         ////
 
--// restriction provided that this copyright statement is not    ////
 
--// removed from the file and that any derivative work contains  ////
 
--// the original copyright notice and the associated disclaimer. ////
 
--//                                                              ////
 
--// This source file is free software; you can redistribute it   ////
 
--// and/or modify it under the terms of the GNU Lesser General   ////
 
--// Public License as published by the Free Software Foundation; ////
 
--// either version 2.1 of the License, or (at your option) any   ////
 
--// later version.                                               ////
 
--//                                                              ////
 
--// This source is distributed in the hope that it will be       ////
 
--// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
--// PURPOSE. See the GNU Lesser General Public License for more  ////
 
--// details.                                                     ////
 
--//                                                              ////
 
--// You should have received a copy of the GNU Lesser General    ////
 
--// Public License along with this source; if not, download it   ////
 
--// from <http://www.opencores.org/lgpl.shtml>                   ////
 
--//                                                              ////
 
--////////////////////////////////////////////////////////////////////
 
--//
 
--// \$Id\$  TAKE OUT THE \'s and this comment in order to get this to work
 
--//
 
--// CVS Revision History
 
--//
 
--// \$Log\$  TAKE OUT THE \'s and this comment in order to get this to work
 
--//
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use std.textio.all; --  Imports the standard textio package.
--library unisim;
 
--use unisim.vcomponents.all;
 
 
 
 
 
entity hitter_wrapper is
entity hitter_wrapper is
port (
     end hitter_wrapper;
 
 
 
     architecture behaviour of hitter_wrapper is
 
        component hitter_sim
 
           port( RX_CLK: in std_logic;
        PUSH_BUTTONS_5BITS_TRI_I: in std_logic_vector(4 downto 0);
        PUSH_BUTTONS_5BITS_TRI_I: in std_logic_vector(4 downto 0);
        LEDS_POSITIONS_TRI_O: out std_logic_vector(4 downto 0)
        LEDS_POSITIONS_TRI_O: out std_logic_vector(4 downto 0)
);
);
end hitter_wrapper;
        end component;
 
        for hitter_sim_0: hitter_sim use entity work.hitter_sim;
architecture implementation of hitter_wrapper is
        signal RX_CLK: std_logic;
 
        signal PUSH_BUTTONS_5BITS_TRI_I: std_logic_vector(4 downto 0);
 
        signal LEDS_POSITIONS_TRI_O: std_logic_vector(4 downto 0);
begin
begin
        LEDS_POSITIONS_TRI_O(0) <= PUSH_BUTTONS_5BITS_TRI_I(1);
        hitter_sim_0: hitter_sim port map (
        LEDS_POSITIONS_TRI_O(1) <= PUSH_BUTTONS_5BITS_TRI_I(2);
                         RX_CLK => RX_CLK,
        LEDS_POSITIONS_TRI_O(2) <= PUSH_BUTTONS_5BITS_TRI_I(3);
                         PUSH_BUTTONS_5BITS_TRI_I => PUSH_BUTTONS_5BITS_TRI_I,
        LEDS_POSITIONS_TRI_O(3) <= PUSH_BUTTONS_5BITS_TRI_I(4);
                         LEDS_POSITIONS_TRI_O => LEDS_POSITIONS_TRI_O );
        LEDS_POSITIONS_TRI_O(4) <= PUSH_BUTTONS_5BITS_TRI_I(0);
        process
 
           variable l : line;
 
           variable counted : integer;
 
        begin
 
           write (l, String'("Exercising hitter_sim"));
 
           writeline (output, l);
 
 
 
           RX_CLK <= '0';
 
           wait for 1 ns;
 
 
end implementation;
           for counted in 0 to 30 loop
 
              -- Instruct:
 
 
 
              if (counted = 2) then
 
                 PUSH_BUTTONS_5BITS_TRI_I <= std_logic_vector'("11111");
 
              else
 
                 PUSH_BUTTONS_5BITS_TRI_I <= std_logic_vector'("00000");
 
              end if;
 
 
 
              RX_CLK <= '1';
 
              wait for 1 ns;
 
 
 
              -- Report:
 
              write (l, String'("Count:"));
 
              write(l, counted);
 
              write (l, String'(" LEDs: "));
 
              for i in LEDS_POSITIONS_TRI_O'range loop
 
                 case LEDS_POSITIONS_TRI_O(i) is
 
                    when '1' => write(l, character'('1'));
 
                    when others => write(l, character'('0'));
 
                 end case;
 
              end loop;
 
              writeline(output, l);
 
 
 
              -- Reset:
 
              RX_CLK <= '0';
 
              wait for 1 ns;
 
           end loop;
 
 
 
           write (l, String'("Done hitter_sim"));
 
           writeline (output, l);
 
           wait;
 
        end process;
 
     end behaviour;
 
 
 
 
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