| Line 7... |
Line 7... |
set_property CFGBVS VCCO [current_design]
|
set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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|
|
## Clock signal
|
## Clock signal
|
|
|
set_property PACKAGE_PIN E3 [get_ports i_clk_100mhz]
|
set_property PACKAGE_PIN E3 [get_ports {sys_clk_i}]
|
set_property IOSTANDARD LVCMOS33 [get_ports i_clk_100mhz]
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set_property IOSTANDARD LVCMOS33 [get_ports {sys_clk_i}]
|
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk_100mhz]
|
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports {sys_clk_i}]
|
|
|
##Switches
|
##Switches
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|
|
set_property PACKAGE_PIN A8 [get_ports {i_sw[0]}]
|
set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports {i_sw[0]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[0]}]
|
set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports {i_sw[1]}]
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set_property PACKAGE_PIN C11 [get_ports {i_sw[1]}]
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set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports {i_sw[2]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[1]}]
|
set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports {i_sw[3]}]
|
set_property PACKAGE_PIN C10 [get_ports {i_sw[2]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[2]}]
|
|
set_property PACKAGE_PIN A10 [get_ports {i_sw[3]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[3]}]
|
|
|
|
##RGB LEDs
|
##RGB LEDs
|
|
|
set_property PACKAGE_PIN E1 [get_ports {o_clr_led0[0]}]
|
set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led0[0]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led0[0]}]
|
set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led0[1]}]
|
set_property PACKAGE_PIN F6 [get_ports {o_clr_led0[1]}]
|
set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led0[2]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led0[1]}]
|
set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led1[0]}]
|
set_property PACKAGE_PIN G6 [get_ports {o_clr_led0[2]}]
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set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led1[1]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led0[2]}]
|
set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led1[2]}]
|
set_property PACKAGE_PIN G4 [get_ports {o_clr_led1[0]}]
|
set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led2[0]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led1[0]}]
|
set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led2[1]}]
|
set_property PACKAGE_PIN J4 [get_ports {o_clr_led1[1]}]
|
set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led2[2]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led1[1]}]
|
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led3[0]}]
|
set_property PACKAGE_PIN G3 [get_ports {o_clr_led1[2]}]
|
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led3[1]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led1[2]}]
|
set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports {o_clr_led3[2]}]
|
set_property PACKAGE_PIN H4 [get_ports {o_clr_led2[0]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led2[0]}]
|
|
set_property PACKAGE_PIN J2 [get_ports {o_clr_led2[1]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led2[1]}]
|
|
set_property PACKAGE_PIN J3 [get_ports {o_clr_led2[2]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led2[2]}]
|
|
set_property PACKAGE_PIN K2 [get_ports {o_clr_led3[0]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led3[0]}]
|
|
set_property PACKAGE_PIN H6 [get_ports {o_clr_led3[1]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led3[1]}]
|
|
set_property PACKAGE_PIN K1 [get_ports {o_clr_led3[2]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led3[2]}]
|
|
|
|
##LEDs
|
##LEDs
|
|
|
set_property PACKAGE_PIN H5 [get_ports {o_led[0]}]
|
set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports {o_led[0]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[0]}]
|
set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports {o_led[1]}]
|
set_property PACKAGE_PIN J5 [get_ports {o_led[1]}]
|
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports {o_led[2]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[1]}]
|
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports {o_led[3]}]
|
set_property PACKAGE_PIN T9 [get_ports {o_led[2]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[2]}]
|
|
set_property PACKAGE_PIN T10 [get_ports {o_led[3]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[3]}]
|
|
|
|
##Buttons
|
##Buttons
|
|
|
set_property PACKAGE_PIN D9 [get_ports {i_btn[0]}]
|
set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports {i_btn[0]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[0]}]
|
set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports {i_btn[1]}]
|
set_property PACKAGE_PIN C9 [get_ports {i_btn[1]}]
|
set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports {i_btn[2]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[1]}]
|
set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports {i_btn[3]}]
|
set_property PACKAGE_PIN B9 [get_ports {i_btn[2]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[2]}]
|
|
set_property PACKAGE_PIN B8 [get_ports {i_btn[3]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[3]}]
|
|
|
|
##Pmod Header JA: PModCLS (bottom)
|
##Pmod Header JA: PModCLS (bottom)
|
|
|
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
|
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
|
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
|
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
|
| Line 84... |
Line 60... |
#-- set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { i_cls_miso }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
|
#-- set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { i_cls_miso }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
|
#-- set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { o_cls_sck }]; #IO_25_15 Sch=ja[10]
|
#-- set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { o_cls_sck }]; #IO_25_15 Sch=ja[10]
|
|
|
##Pmod Header JB: OLEDrgb
|
##Pmod Header JB: OLEDrgb
|
|
|
set_property PACKAGE_PIN E15 [get_ports o_oled_cs_n]
|
set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports o_oled_cs_n]
|
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_cs_n]
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set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports o_oled_mosi]
|
set_property PACKAGE_PIN E16 [get_ports o_oled_mosi]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_mosi]
|
|
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { i_oled_nc }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
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#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { i_oled_nc }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
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set_property PACKAGE_PIN C15 [get_ports o_oled_sck]
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set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports o_oled_sck]
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set_property IOSTANDARD LVCMOS33 [get_ports o_oled_sck]
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set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports o_oled_dcn]
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set_property PACKAGE_PIN J17 [get_ports o_oled_dcn]
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set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports o_oled_reset_n]
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set_property IOSTANDARD LVCMOS33 [get_ports o_oled_dcn]
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set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports o_oled_vccen]
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set_property PACKAGE_PIN J18 [get_ports o_oled_reset_n]
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set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports o_oled_pmoden]
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set_property IOSTANDARD LVCMOS33 [get_ports o_oled_reset_n]
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|
set_property PACKAGE_PIN K15 [get_ports o_oled_vccen]
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set_property IOSTANDARD LVCMOS33 [get_ports o_oled_vccen]
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set_property PACKAGE_PIN J15 [get_ports o_oled_pmoden]
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set_property IOSTANDARD LVCMOS33 [get_ports o_oled_pmoden]
|
|
|
|
##Pmod Header JC: GPS (top), UART (bottom)
|
##Pmod Header JC: GPS (top), UART (bottom)
|
|
|
set_property PACKAGE_PIN U12 [get_ports i_gps_3df]
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set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports i_gps_3df]
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set_property IOSTANDARD LVCMOS33 [get_ports i_gps_3df]
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set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports o_gps_tx]
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set_property PACKAGE_PIN V12 [get_ports o_gps_tx]
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set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports i_gps_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports o_gps_tx]
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set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports i_gps_pps]
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set_property PACKAGE_PIN V10 [get_ports i_gps_rx]
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set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports i_aux_rts]
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set_property IOSTANDARD LVCMOS33 [get_ports i_gps_rx]
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set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports o_aux_tx]
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set_property PACKAGE_PIN V11 [get_ports i_gps_pps]
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set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports i_aux_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports i_gps_pps]
|
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports o_aux_cts]
|
set_property PACKAGE_PIN U14 [get_ports i_aux_rts]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports i_aux_rts]
|
|
set_property PACKAGE_PIN V14 [get_ports o_aux_tx]
|
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set_property IOSTANDARD LVCMOS33 [get_ports o_aux_tx]
|
|
set_property PACKAGE_PIN T13 [get_ports i_aux_rx]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports i_aux_rx]
|
|
set_property PACKAGE_PIN U13 [get_ports o_aux_cts]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports o_aux_cts]
|
|
|
|
##Pmod Header JD: SD-Card
|
##Pmod Header JD: SD-Card
|
|
|
set_property PACKAGE_PIN D4 [get_ports {io_sd[3]}]
|
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports {io_sd[3]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[3]}]
|
set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports io_sd_cmd]
|
set_property PACKAGE_PIN D3 [get_ports io_sd_cmd]
|
set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports {io_sd[0]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports io_sd_cmd]
|
set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports o_sd_sck]
|
set_property PACKAGE_PIN F4 [get_ports {io_sd[0]}]
|
set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports {io_sd[1]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[0]}]
|
set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports {io_sd[2]}]
|
set_property PACKAGE_PIN F3 [get_ports o_sd_sck]
|
set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports i_sd_cs]
|
set_property IOSTANDARD LVCMOS33 [get_ports o_sd_sck]
|
set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports i_sd_wp]
|
set_property PACKAGE_PIN E2 [get_ports {io_sd[1]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[1]}]
|
|
set_property PACKAGE_PIN D2 [get_ports {io_sd[2]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[2]}]
|
|
set_property PACKAGE_PIN H2 [get_ports i_sd_cs]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports i_sd_cs]
|
|
set_property PACKAGE_PIN G2 [get_ports i_sd_wp]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports i_sd_wp]
|
|
|
|
##USB-UART Interface
|
##USB-UART Interface
|
# THESE ARE CORRECT
|
# THESE ARE CORRECT
|
set_property PACKAGE_PIN D10 [get_ports o_uart_tx]
|
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx]
|
set_property IOSTANDARD LVCMOS33 [get_ports o_uart_tx]
|
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports i_uart_rx]
|
set_property PACKAGE_PIN A9 [get_ports i_uart_rx]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports i_uart_rx]
|
|
#
|
#
|
|
|
##ChipKit Single Ended Analog Inputs
|
##ChipKit Single Ended Analog Inputs
|
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
|
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
|
## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
|
## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
|
| Line 236... |
Line 187... |
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
|
|
##Misc. ChipKit signals
|
##Misc. ChipKit signals
|
|
|
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
set_property PACKAGE_PIN C2 [get_ports i_reset_btn]
|
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports i_reset_btn]
|
set_property IOSTANDARD LVCMOS33 [get_ports i_reset_btn]
|
|
|
|
##SMSC Ethernet PHY
|
##SMSC Ethernet PHY
|
|
|
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { i_eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { i_eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
set_property PACKAGE_PIN F16 [get_ports o_eth_mdclk]
|
set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports o_eth_mdclk]
|
set_property IOSTANDARD LVCMOS33 [get_ports o_eth_mdclk]
|
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports io_eth_mdio]
|
set_property PACKAGE_PIN K13 [get_ports io_eth_mdio]
|
set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { o_eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
set_property IOSTANDARD LVCMOS33 [get_ports io_eth_mdio]
|
set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { o_eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { i_eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { i_eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { i_eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { i_eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { i_eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { i_eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { i_eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { i_eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { o_eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { o_eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { o_eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { o_eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { o_eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
|
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
# Ethernet generated clocks from the chip
|
|
create_clock -period 40.000 -name eth_tx_pin -add [get_ports {i_eth_tx_clk}]
|
|
create_clock -period 40.000 -name eth_rx_pin -add [get_ports {i_eth_rx_clk}]
|
|
|
|
# And crossing clocks from ethernet clocks to master clock
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/o_net_reset*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_rx_clear*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_tx_busy*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_tx_busy*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txpadi/o_v*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_tx_busy*}] 12.3;
|
|
# set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tx_len*}] -to [get_cells -hier -filter {NAME =~ *netctrl/n_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/config_*}] -to [get_cells -hier -filter {NAME =~ *netctrl/n_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tx_cm*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_tx_cm*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tx_cancel*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_tx_cancel*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/hw_mac*}] -to [get_cells -hier -filter {NAME =~ *netctrl/txmaci/r_hw*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/hw_mac*}] -to [get_cells -hier -filter {NAME =~ *netctrl/rxmaci/r_hw*}] 12.3;
|
|
# set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_*}] -to [get_cells -hier -filter {NAME =~ *net_scope/mem*}] 12.3;
|
|
# set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txprei/r_*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txprei/r_*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txprei/r_*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txmaci/o_*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txpadi/o_*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txcrci/o_v*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_tx_busy*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txpadi/o_v*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_tx_busy*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_rx_val*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_rx_val*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_rx_busy*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_rx_busy*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_rx_len*}] -to [get_cells -hier -filter {NAME =~ *netctrl/rx_len*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_rx_miss*}] -to [get_cells -hier -filter {NAME =~ *netctrl/rx_miss_pi*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/p_rx_cle*}] -to [get_cells -hier -filter {NAME =~ *netctrl/r_rx_clear*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_rx_crce*}] -to [get_cells -hier -filter {NAME =~ *netctrl/rx_crc_pip*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_rx_err*}] -to [get_cells -hier -filter {NAME =~ *netctrl/rx_err_pip*}] 12.3;
|
|
|
|
# and for the scope ... if we have that configured
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/br_config*}] -to [get_cells -hier -filter {NAME =~ *net_scope/mem*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/br_config*}] -to [get_cells -hier -filter {NAME =~ *net_scope/waddr*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/br_config*}] -to [get_cells -hier -filter {NAME =~ *net_scope/counter*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/br_config*}] -to [get_cells -hier -filter {NAME =~ *net_scope/dr_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/br_config*}] -to [get_cells -hier -filter {NAME =~ *net_scope/q_if*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/r_rese*}] -to [get_cells -hier -filter {NAME =~ *net_scope/q_rese*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/waddr*}] -to [get_cells -hier -filter {NAME =~ *net_scope/mem*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *net_scope/dr_*}] -to [get_cells -hier -filter {NAME =~ *net_scope/q_of*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxmaci/o_d*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxmaci/r_err*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxememi/o_v*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxprei/o_d*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxprei/o_v*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxmaci*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxmaci/o_broa*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxcrci/o_d*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/rxcrci/o_v*}] -to [get_cells -hier -filter {NAME =~ *net_scope/o_wb_data*}] 12.3;
|
|
|
##Quad SPI Flash
|
##Quad SPI Flash
|
|
|
set_property PACKAGE_PIN L13 [get_ports o_qspi_cs_n]
|
set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports o_qspi_cs_n]
|
set_property IOSTANDARD LVCMOS33 [get_ports o_qspi_cs_n]
|
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {io_qspi_dat[0]}]
|
set_property PACKAGE_PIN K17 [get_ports {io_qspi_dat[0]}]
|
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {io_qspi_dat[1]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[0]}]
|
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports {io_qspi_dat[2]}]
|
set_property PACKAGE_PIN K18 [get_ports {io_qspi_dat[1]}]
|
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports {io_qspi_dat[3]}]
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[1]}]
|
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports o_qspi_sck]
|
set_property PACKAGE_PIN L14 [get_ports {io_qspi_dat[2]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[2]}]
|
|
set_property PACKAGE_PIN M14 [get_ports {io_qspi_dat[3]}]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[3]}]
|
|
set_property PACKAGE_PIN L16 [get_ports o_qspi_sck]
|
|
set_property IOSTANDARD LVCMOS33 [get_ports o_qspi_sck]
|
|
|
|
##Power Measurements
|
##Power Measurements
|
|
|
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
| Line 290... |
Line 283... |
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
|
|
## Memory
|
## Memory
|
|
|
# Memory address lines
|
|
set_property PACKAGE_PIN R2 [get_ports {o_ddr_addr[0]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[0]}]
|
|
set_property PACKAGE_PIN M6 [get_ports {o_ddr_addr[1]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[1]}]
|
|
set_property PACKAGE_PIN N4 [get_ports {o_ddr_addr[2]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[2]}]
|
|
set_property PACKAGE_PIN T1 [get_ports {o_ddr_addr[3]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[3]}]
|
|
set_property PACKAGE_PIN N6 [get_ports {o_ddr_addr[4]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[4]}]
|
|
set_property PACKAGE_PIN R7 [get_ports {o_ddr_addr[5]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[5]}]
|
|
set_property PACKAGE_PIN V6 [get_ports {o_ddr_addr[6]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[6]}]
|
|
set_property PACKAGE_PIN U7 [get_ports {o_ddr_addr[7]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[7]}]
|
|
set_property PACKAGE_PIN R8 [get_ports {o_ddr_addr[8]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[8]}]
|
|
set_property PACKAGE_PIN V7 [get_ports {o_ddr_addr[9]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[9]}]
|
|
set_property PACKAGE_PIN R6 [get_ports {o_ddr_addr[10]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[10]}]
|
|
set_property PACKAGE_PIN U6 [get_ports {o_ddr_addr[11]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[11]}]
|
|
set_property PACKAGE_PIN T6 [get_ports {o_ddr_addr[12]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[12]}]
|
|
set_property PACKAGE_PIN T8 [get_ports {o_ddr_addr[13]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[13]}]
|
|
set_property PACKAGE_PIN R1 [get_ports {o_ddr_ba[0]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_ba[0]}]
|
|
set_property PACKAGE_PIN P4 [get_ports {o_ddr_ba[1]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_ba[1]}]
|
|
set_property PACKAGE_PIN P2 [get_ports {o_ddr_ba[2]}]
|
|
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_ba[2]}]
|
|
#
|
#
|
set_property PACKAGE_PIN M4 [get_ports o_ddr_cas_n]
|
# While valid definitions below, these definitions conflict with the XDC file
|
set_property IOSTANDARD SSTL135 [get_ports o_ddr_cas_n]
|
# created by the Memory Interface Generator (MIG), and so these have been
|
# Clock lines
|
# commented out.
|
set_property IOSTANDARD DIFF_SSTL135 [get_ports o_ddr_ck_n]
|
#
|
set_property PACKAGE_PIN U9 [get_ports o_ddr_ck_p]
|
## Memory address lines
|
set_property IOSTANDARD DIFF_SSTL135 [get_ports o_ddr_ck_p]
|
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[0]}]
|
|
#set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[1]}]
|
|
#set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[2]}]
|
|
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[3]}]
|
|
#set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[4]}]
|
|
#set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[5]}]
|
|
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[6]}]
|
|
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[7]}]
|
|
#set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[8]}]
|
|
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[9]}]
|
|
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[10]}]
|
|
#set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[11]}]
|
|
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[12]}]
|
|
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_addr[13]}]
|
|
#set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_ba[0]}]
|
|
#set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_ba[1]}]
|
|
#set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_ba[2]}]
|
|
#
|
|
## Clock lines
|
|
#
|
|
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD DIFF_SSTL135 SLEW FAST } [get_ports {ddr3_ck_p[0]}]
|
|
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD DIFF_SSTL135 SLEW FAST } [get_ports {ddr3_ck_n[0]}]
|
#
|
#
|
set_property PACKAGE_PIN N5 [get_ports o_ddr_cke]
|
##
|
set_property IOSTANDARD SSTL135 [get_ports o_ddr_cke]
|
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_dm[0]}]
|
set_property PACKAGE_PIN U8 [get_ports o_ddr_cs_n]
|
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_dm[1]}]
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set_property IOSTANDARD SSTL135 [get_ports o_ddr_cs_n]
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## Data (DQ) lines
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set_property PACKAGE_PIN L1 [get_ports {o_ddr_dm[0]}]
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#set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {o_ddr_dm[0]}]
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#set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[1]}]
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set_property PACKAGE_PIN U1 [get_ports {o_ddr_dm[1]}]
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#set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {o_ddr_dm[1]}]
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#set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[3]}]
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# Data (DQ) lines
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#set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[4]}]
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set_property PACKAGE_PIN K5 [get_ports {io_ddr_data[0]}]
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#set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[0]}]
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#set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[6]}]
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set_property PACKAGE_PIN L3 [get_ports {io_ddr_data[1]}]
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#set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[1]}]
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#set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[8]}]
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set_property PACKAGE_PIN K3 [get_ports {io_ddr_data[2]}]
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#set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[2]}]
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#set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[10]}]
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set_property PACKAGE_PIN L6 [get_ports {io_ddr_data[3]}]
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#set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[3]}]
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#set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[12]}]
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set_property PACKAGE_PIN M3 [get_ports {io_ddr_data[4]}]
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#set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[4]}]
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#set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[14]}]
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set_property PACKAGE_PIN M1 [get_ports {io_ddr_data[5]}]
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#set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[5]}]
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set_property PACKAGE_PIN L4 [get_ports {io_ddr_data[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[6]}]
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set_property PACKAGE_PIN M2 [get_ports {io_ddr_data[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[7]}]
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set_property PACKAGE_PIN V4 [get_ports {io_ddr_data[8]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[8]}]
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set_property PACKAGE_PIN T5 [get_ports {io_ddr_data[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[9]}]
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set_property PACKAGE_PIN U4 [get_ports {io_ddr_data[10]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[10]}]
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set_property PACKAGE_PIN V5 [get_ports {io_ddr_data[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[11]}]
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set_property PACKAGE_PIN V1 [get_ports {io_ddr_data[12]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[12]}]
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set_property PACKAGE_PIN T3 [get_ports {io_ddr_data[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[13]}]
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set_property PACKAGE_PIN U3 [get_ports {io_ddr_data[14]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[14]}]
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set_property PACKAGE_PIN R3 [get_ports {io_ddr_data[15]}]
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set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[15]}]
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# DQS
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# DQS
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_n[0]}]
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#set_property -dict { PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dqs_p[0]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_n[1]}]
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#set_property -dict { PACKAGE_PIN U2 IOSTANDARD DIFF_SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dqs_p[1]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_p[0]}]
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#set_property -dict { PACKAGE_PIN N1 IOSTANDARD DIFF_SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dqs_n[0]}]
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set_property PACKAGE_PIN N2 [get_ports {io_ddr_dqs_p[0]}]
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#set_property -dict { PACKAGE_PIN V2 IOSTANDARD DIFF_SSTL135 SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports {ddr3_dqs_n[1]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_p[1]}]
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## Command wires
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set_property PACKAGE_PIN U2 [get_ports {io_ddr_dqs_p[1]}]
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#set_property -dict { PACKAGE_PIN K6 IOSTANDARD SSTL135 SLEW FAST } [get_ports ddr3_reset_n]
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set_property PACKAGE_PIN R5 [get_ports o_ddr_odt]
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#set_property -dict { PACKAGE_PIN N5 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL135 [get_ports o_ddr_odt]
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#set_property -dict { PACKAGE_PIN U8 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_cs_n[0]}]
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set_property PACKAGE_PIN P3 [get_ports o_ddr_ras_n]
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#set_property -dict { PACKAGE_PIN P3 IOSTANDARD SSTL135 SLEW FAST } [get_ports ddr3_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports o_ddr_ras_n]
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#set_property -dict { PACKAGE_PIN M4 IOSTANDARD SSTL135 SLEW FAST } [get_ports ddr3_cas_n]
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set_property PACKAGE_PIN K6 [get_ports o_ddr_reset_n]
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#set_property -dict { PACKAGE_PIN P5 IOSTANDARD SSTL135 SLEW FAST } [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL135 [get_ports o_ddr_reset_n]
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#set_property -dict { PACKAGE_PIN R5 IOSTANDARD SSTL135 SLEW FAST } [get_ports {ddr3_odt[0]}]
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set_property PACKAGE_PIN P5 [get_ports o_ddr_we_n]
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##Internal VREF
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set_property IOSTANDARD SSTL135 [get_ports o_ddr_we_n]
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#Internal VREF
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set_property INTERNAL_VREF 0.675 [get_iobanks 34]
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set_property INTERNAL_VREF 0.675 [get_iobanks 34]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property BITSTREAM.CONFIG.CCLKPIN PULLNONE [current_design]
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set_property BITSTREAM.CONFIG.CCLKPIN PULLNONE [current_design]
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