| Line 95... |
Line 95... |
|
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This means not using the Memory Interface Generator (MIG), the
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This means not using the Memory Interface Generator (MIG), the
|
Xilinx CoreGen IP, etc. Further, I wish to use all of Arty's on--board
|
Xilinx CoreGen IP, etc. Further, I wish to use all of Arty's on--board
|
hardware: Flash, DDR3-SDRAM, Ethernet, and everything else at their
|
hardware: Flash, DDR3-SDRAM, Ethernet, and everything else at their
|
full and fastest speed(s). For example, the flash will need to be
|
full and fastest speed(s). For example, the flash will need to be
|
clocked at 100~MHz, not the 50~MHz I've clocked it at before. The
|
clocked at 82~MHz, not the 50~MHz I've clocked it at before. The
|
memory should also be able to support pipelined 32--bit interactions
|
memory should also be able to support pipelined 32--bit interactions
|
over the Wishbone bus at a 200~MHz clock. Finally, the Ethernet
|
over the Wishbone bus at a 162~MHz clock. Finally, the Ethernet
|
controller should be supported by a DMA capable interface that can
|
controller should be supported by a DMA capable interface that can
|
drive the ethernet at its full 100Mbps rate.
|
drive the ethernet at its full 100Mbps rate.
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|
|
\item Run using a 200~MHz clock, if for no other reason than to gain the
|
\item Run using a 162.5~MHz clock, if for no other reason than to gain the
|
experience of building logic that can run that fast.
|
experience of building logic that can run that fast.\footnote{The
|
|
original goal was to run at 200~MHz. However, the memory controller
|
|
cannot run faster than 83~MHz. If we run it at 81.25~MHz and double
|
|
that clock to get our logic clock, that now places us at 162.5~MHz.
|
|
200~MHz is \ldots too fast for DDR3 transfers using the Artix--7 chip
|
|
on the Arty.}
|
|
|
\item Modify the ZipCPU to support an MMU and a data cache, and perhaps even
|
\item Modify the ZipCPU to support an MMU and a data cache, and perhaps even
|
a floating point unit.
|
a floating point unit.
|
|
|
\item The default configuration will also include three Pmods: a USBUART,
|
\item The default configuration will also include three Pmods: a USBUART,
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| Line 185... |
Line 190... |
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 000x xxxx} & \scalebox{0.9}{\tt 0x00000100} & \hfill 32 & Peripheral I/O Control \\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 000x xxxx} & \scalebox{0.9}{\tt 0x00000100} & \hfill 32 & Peripheral I/O Control \\\hline
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\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 0yyx} & \scalebox{0.9}{\tt 0x00000120} & \hfill 8 & Debug scope control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 0yyx} & \scalebox{0.9}{\tt 0x00000120} & \hfill 8 & Debug scope control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 10xx} & \scalebox{0.9}{\tt 0x00000128} & \hfill 4 & RTC control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 10xx} & \scalebox{0.9}{\tt 0x00000128} & \hfill 4 & RTC control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 11xx} & \scalebox{0.9}{\tt 0x0000012c} & \hfill 4 & SDCard controller\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 11xx} & \scalebox{0.9}{\tt 0x0000012c} & \hfill 4 & SDCard controller\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 00xx} & \scalebox{0.9}{\tt 0x00000130} & \hfill 4 & GPS Clock loop control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 00xx} & \scalebox{0.9}{\tt 0x00000130} & \hfill 4 & GPS Clock loop control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 01xx} & \scalebox{0.9}{\tt 0x00000134} & \hfill 4 & Network packet interface\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 01xx} & \scalebox{0.9}{\tt 0x00000134} & \hfill 4 & OLEDrgb control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 10xx} & \scalebox{0.9}{\tt 0x00000138} & \hfill 4 & OLEDrgb control\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 1xxx} & \scalebox{0.9}{\tt 0x00000138} & \hfill 8 & Network packet interface\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 11xx} & \scalebox{0.9}{\tt 0x0000013c} & \hfill 4 & {\em Unused}\\\hline
|
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0100 0xxx} & \scalebox{0.9}{\tt 0x00000140} & \hfill 8 & GPS Testbench\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0100 0xxx} & \scalebox{0.9}{\tt 0x00000140} & \hfill 8 & GPS Testbench\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0100 1xxx} & \scalebox{0.9}{\tt 0x00000148} & \hfill 8 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0100 1xxx} & \scalebox{0.9}{\tt 0x00000148} & \hfill 8 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0101 xxxx} & \scalebox{0.9}{\tt 0x00000150} & \hfill 16 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0101 xxxx} & \scalebox{0.9}{\tt 0x00000150} & \hfill 16 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 011x xxxx} & \scalebox{0.9}{\tt 0x00000160} & \hfill 32 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 011x xxxx} & \scalebox{0.9}{\tt 0x00000160} & \hfill 32 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 100x xxxx} & \scalebox{0.9}{\tt 0x00000180} & \hfill 32 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 100x xxxx} & \scalebox{0.9}{\tt 0x00000180} & \hfill 32 & {\em Unused}\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 101x xxxx} & \scalebox{0.9}{\tt 0x000001a0} & \hfill 32 & Ethernet configuration registers\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 101x xxxx} & \scalebox{0.9}{\tt 0x000001a0} & \hfill 32 & Ethernet configuration registers\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 110x xxxx} & \scalebox{0.9}{\tt 0x000001c0} & \hfill 32 & Extended Flash Control Port\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 110x xxxx} & \scalebox{0.9}{\tt 0x000001c0} & \hfill 32 & Extended Flash Control Port\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 111x xxxx} & \scalebox{0.9}{\tt 0x000001e0} & \hfill 32 & ICAPE2 Configuration Port\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 111x xxxx} & \scalebox{0.9}{\tt 0x000001e0} & \hfill 32 & ICAPE2 Configuration Port\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 10xx xxxx xxxx} & \scalebox{0.9}{\tt 0x00000800} & \hfill 1k & Ethernet TX Buffer\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 10xx xxxx xxxx} & \scalebox{0.9}{\tt 0x00000800} & \hfill 1k & Ethernet RX Buffer\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 11xx xxxx xxxx} & \scalebox{0.9}{\tt 0x00000c00} & \hfill 1k & Ethernet RX Buffer\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 0000 11xx xxxx xxxx} & \scalebox{0.9}{\tt 0x00000c00} & \hfill 1k & Ethernet TX Buffer\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 1xxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x00008000} & \hfill 32k & On-chip Block RAM\\\hline
|
\scalebox{0.9}{\tt 0000 0000 0000 1xxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x00008000} & \hfill 32k & On-chip Block RAM\\\hline
|
\scalebox{0.9}{\tt 0000 01xx xxxx xxxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x00400000} & \hfill 4M & QuadSPI Flash\\\hline
|
\scalebox{0.9}{\tt 0000 01xx xxxx xxxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x00400000} & \hfill 4M & QuadSPI Flash\\\hline
|
|
\scalebox{0.9}{\tt 0000 0100 0000 0000 0000 0000 0000} & \scalebox{0.9}{\tt 0x00400000} & & Configuration Start\\\hline
|
|
\scalebox{0.9}{\tt 0000 0100 0111 0000 0000 0000 0000} & \scalebox{0.9}{\tt 0x00470000} & & Alternate Configuration\\\hline
|
|
\scalebox{0.9}{\tt 0000 0100 1110 0000 0000 0000 0000} & \scalebox{0.9}{\tt 0x004e0000} & & CPU Reset Address\\\hline
|
\scalebox{0.9}{\tt 01xx xxxx xxxx xxxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x04000000} & \hfill 64M & DDR3 SDRAM\\\hline
|
\scalebox{0.9}{\tt 01xx xxxx xxxx xxxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x04000000} & \hfill 64M & DDR3 SDRAM\\\hline
|
\scalebox{0.9}{\tt 1000 0000 0000 0000 0000 0000 000x} & \scalebox{0.9}{\tt 0x08000000} & \hfill 2 & ZipCPU debug control port---only visible to debug WB master\\\hline
|
\scalebox{0.9}{\tt 1000 0000 0000 0000 0000 0000 000x} & \scalebox{0.9}{\tt 0x08000000} & \hfill 2 & ZipCPU debug control port---only visible to debug WB master\\\hline
|
\end{tabular}
|
\end{tabular}
|
\caption{Address Regions}\label{tbl:memregions}
|
\caption{Address Regions}\label{tbl:memregions}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
| Line 380... |
Line 387... |
% 0x010c-0x010f
|
% 0x010c-0x010f
|
\end{reglist}
|
\end{reglist}
|
\caption{Flash control registers}\label{tbl:flctl}
|
\caption{Flash control registers}\label{tbl:flctl}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
|
|
\chapter{Wishbone}
|
\chapter{Wishbone Datasheet}\label{ch:wishbone}
|
|
|
The master and slave interfaces have been simplified with the following
|
The master and slave interfaces have been simplified with the following
|
requirement: the {\tt STB} line is not allowed to be high unless the {\tt CYC}
|
requirement: the {\tt STB} line is not allowed to be high unless the {\tt CYC}
|
line is high. In this fashion, a slave may often be able to ignore {\tt CYC}
|
line is high. In this fashion, a slave may often be able to ignore {\tt CYC}
|
and only act on the presence of {\tt STB}, knowing that {\tt CYC} must be
|
and only act on the presence of {\tt STB}, knowing that {\tt CYC} must be
|
active at the same time.
|
active at the same time.
|
|
|
\chapter{Clocks}
|
\chapter{Clocks}\label{ch:clocks}
|
\begin{table}\begin{center}
|
\begin{table}\begin{center}
|
\begin{clocklist}
|
\begin{clocklist}
|
{\tt i\_clk\_100mhz} & Ext & \multicolumn{2}{c|}{100~MHz} &
|
{\tt i\_clk\_100mhz} & Ext & \multicolumn{2}{c|}{100} &
|
100~MHz Crystal Oscillator \\\hline
|
100~MHz Crystal Oscillator \\\hline
|
{\tt s\_clk} & PLL & 200~MHz & & Internal Logic, Wishbone Clock \\\hline
|
{\em Future }{\tt s\_clk} & PLL & 152 & 166 & Internal Logic, Wishbone Clock \\\hline
|
{\tt ram\_clk} & PLL & 200~MHz & & DDR3 SDRAM Clock \\\hline
|
{\tt s\_clk} & PLL & 83.33 & 75.76& DDR3 SDRAM Controller Clock \\\hline
|
{\tt o\_sck} & Logic & 108~MHz & 50~MHz & QSPI Flash clock \\\hline
|
\multicolumn{2}{|c|}{\tt mem\_clk\_200mhz} & 200~MHz & & MIG Reference clock for PHASERs\\\hline
|
{\tt o\_sdclk} & Logic & 50~MHz & 100~kHz & SD--Card clock \\\hline
|
{\tt ddr3\_ck\_}$x$ & DDR & 166.67 & 303 & DDR3 Command Clock\\\hline
|
|
{\tt o\_qspi\_sck} & DDR & 95 & & QSPI Flash clock \\\hline
|
|
{\tt o\_sd\_clk} & Logic & 50 & 0.100 & SD--Card clock \\\hline
|
|
{\tt o\_oled\_sck} & Logic & 166 & & OLED SPI clock \\\hline
|
|
{\tt o\_eth\_mdclk} & Logic & 25 & 2.5 & Ethernet MDIO controller clock\\\hline
|
\end{clocklist}
|
\end{clocklist}
|
\caption{OpenArty clocks}\label{tbl:clocks}
|
\caption{OpenArty clocks}\label{tbl:clocks}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
|
|
\chapter{I/O Ports}
|
\chapter{I/O Ports}
|
