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[/] [openarty/] [trunk/] [doc/] [src/] [spec.tex] - Diff between revs 48 and 49
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{\tt SDCARD\_ACCESS}, and {\tt OLEDRGBACCESS} found in the {\tt rtl/busmaster.v}
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{\tt SDCARD\_ACCESS}, and {\tt OLEDRGBACCESS} found in the {\tt rtl/busmaster.v}
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file. This will recover all but the logic used by the PModUSBUART and PModGPS
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file. This will recover all but the logic used by the PModUSBUART and PModGPS
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serial ports, while replacing the registers with read--only memory values of
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serial ports, while replacing the registers with read--only memory values of
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zero.
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zero.
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The {\tt arty.xdc} file is designed so that these PMods can be connected as
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shown in Fig.~\ref{fig:pmod-pic}.
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\begin{figure}\begin{center}
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\includegraphics[width=4in]{../gfx/openarty.eps}
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\caption{Showing how the PMods are Connected}\label{fig:pmod-pic}
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\end{center}\end{figure}
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In this example, the PModOLED is connected to PMod port JB, and the PModSD is
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connected to PMod port JD. Both the PModGPS and the PModUSBUART are both
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connected to port JC, with the GPS connected on top and the USBUART on the
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bottom.
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\section{Testing the peripherals}
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\section{Testing the peripherals}
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OpenArty has been designed so that all of the peripherals live on a
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OpenArty has been designed so that all of the peripherals live on a
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memory--mapped wishbone bus. This bus can be accessed, either by the ZipCPU
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memory--mapped wishbone bus. This bus can be accessed, either by the ZipCPU
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or by the host controller. Because of this model, peripherals may be tested
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or by the host controller. Because of this model, peripherals may be tested
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