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[/] [openarty/] [trunk/] [rtl/] [bigsub.v] - Diff between revs 3 and 34

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//
//
// Filename:    bigsub.v
// Filename:    bigsub.v
//
//
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
//
//
// Purpose:     
// Purpose:     To subtract two 64-bit numbers, while maintaining
 
//              synchronization to whatever purpose these numbers had
 
//      originally.  For this reason, there is an i_sync input and an o_sync
 
//      output.  If i_sync is true with a particular set of data, o_sync will
 
//      then be true when that data is placed on the output.
 
//
 
//      If we needed to slow this down even more, I suppose we could register
 
//      the inputs before we used them ...
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
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//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
module  bigsub(i_clk, i_sync, i_a, i_b, o_r, o_sync);
module  bigsub(i_clk, i_sync, i_a, i_b, o_r, o_sync);
 
        parameter       NCLOCKS = 1;
        input                   i_clk, i_sync;
        input                   i_clk, i_sync;
        input           [63:0]   i_a, i_b;
        input           [63:0]   i_a, i_b;
        output  reg     [63:0]   o_r;
        output  wire    [63:0]   o_r;
        output  reg     o_sync;
        output  wire    o_sync;
 
 
 
        generate
 
        if (NCLOCKS == 0)
 
        begin
 
                assign  o_sync= i_sync;
 
                assign  o_r = i_a - i_b;
 
        end else if (NCLOCKS == 1)
 
        begin
 
                reg             r_sync;
 
                reg     [63:0]   r_out;
 
                always @(posedge i_clk)
 
                        r_sync <= i_sync;
 
                always @(posedge i_clk)
 
                        r_out <= i_a - i_b;
 
 
 
                assign  o_sync = r_sync;
 
                assign  o_r = r_out;
 
        end else // if (NCLOCKS == 2)
 
        begin
        reg             r_sync, r_pps;
        reg             r_sync, r_pps;
        reg     [31:0]   r_hi_a, r_hi_b, r_low;
                reg     [31:0]   r_hi, r_low;
 
 
 
                reg     [63:0]   f_r;
 
                reg             f_sync;
 
 
 
                wire    [63:0]   i_b_n;
 
                assign          i_b_n = ~i_b;
 
 
        initial r_sync = 1'b0;
        initial r_sync = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_sync <= i_sync;
                r_sync <= i_sync;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                { r_pps, r_low } <= i_a[31:0] + ({1'b1,~i_b[31:0]}) + 1'b1;
                        { r_pps, r_low } <= i_a[31:0] + i_b_n[31:0] + 1'b1;
        always @(posedge i_clk)
 
                r_hi_a <= i_a[63:32];
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_hi_b <= ~i_b[63:32];
                        r_hi <= i_a[63:32] + i_b_n[63:32];
 
 
        initial o_sync = 1'b0;
                initial f_sync = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_sync <= r_sync;
                        f_sync <= r_sync;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_r[31:0] <= r_low;
                        f_r[31:0] <= r_low;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_r[63:32] <= r_hi_a + r_hi_b + { 31'h00, r_pps };
                        f_r[63:32] <= r_hi + { 31'h00, r_pps };
 
 
 
                assign  o_sync = f_sync;
 
                assign  o_r    = f_r;
 
 
 
        end endgenerate
 
 
endmodule
endmodule
 
 
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