| Line 38... |
Line 38... |
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
`define NO_ZIP_WBU_DELAY
|
`define NO_ZIP_WBU_DELAY
|
`define ZIPCPU
|
`define ZIPCPU
|
`ifdef ZIPCPU
|
|
`define ZIP_SYSTEM
|
|
`ifndef ZIP_SYSTEM
|
|
`define ZIP_BONES
|
|
`endif // ZIP_SYSTEM
|
|
`endif // ZipCPU
|
|
//
|
//
|
//
|
//
|
`define SDCARD_ACCESS
|
`define SDCARD_ACCESS
|
`define ETHERNET_ACCESS
|
`define ETHERNET_ACCESS
|
`ifndef VERILATOR
|
`ifndef VERILATOR
|
`define ICAPE_ACCESS
|
`define ICAPE_ACCESS
|
`endif
|
`endif
|
`define FLASH_ACCESS
|
`define FLASH_ACCESS
|
//`define SDRAM_ACCESS
|
`define SDRAM_ACCESS
|
`define GPS_CLOCK
|
`define GPS_CLOCK
|
// UART_ACCESS and GPS_UART have both been placed within fastio
|
// UART_ACCESS and GPS_UART have both been placed within fastio
|
// `define UART_ACCESS
|
// `define UART_ACCESS
|
// `define GPS_UART
|
// `define GPS_UART
|
`define RTC_ACCESS
|
`define RTC_ACCESS
|
`define OLEDRGB_ACCESS
|
`define OLEDRGB_ACCESS
|
//
|
//
|
// `define CPU_SCOPE
|
//
|
// `define GPS_SCOPE
|
//
|
`define FLASH_SCOPE
|
//
|
// `define SDRAM_SCOPE
|
//
|
|
// Now, conditional compilation based upon what capabilities we have turned
|
|
// on
|
|
//
|
|
`ifdef ZIPCPU
|
|
`define ZIP_SYSTEM
|
|
`ifndef ZIP_SYSTEM
|
|
`define ZIP_BONES
|
|
`endif // ZIP_SYSTEM
|
|
`endif // ZipCPU
|
|
//
|
|
//
|
|
// SCOPE POSITION ZERO
|
|
//
|
|
`ifdef FLASH_ACCESS
|
|
`define FLASH_SCOPE // Position zero
|
|
`else
|
|
`ifdef ZIPCPU
|
|
// `define CPU_SCOPE // Position zero
|
|
`endif
|
|
`endif
|
|
//
|
|
// SCOPE POSITION ONE
|
|
//
|
|
// `define GPS_SCOPE // Position one
|
|
`ifdef ICAPE_ACCESS
|
|
`define CFG_SCOPE // Position one
|
|
`endif
|
|
//
|
|
// SCOPE POSITION TWO
|
|
//
|
|
`ifdef SDRAM_ACCESS
|
|
`define SDRAM_SCOPE // Position two
|
|
`endif
|
// `define ENET_SCOPE
|
// `define ENET_SCOPE
|
//
|
//
|
//
|
//
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
// CNC
|
// CNC
|
| Line 78... |
Line 105... |
// PMod I/O
|
// PMod I/O
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
// The Quad SPI Flash
|
// The Quad SPI Flash
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
// The DDR3 SDRAM
|
// The DDR3 SDRAM
|
o_ddr_reset_n, o_ddr_cke,
|
// The actual wires need to be controlled from the device
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
// dependent file. In order to keep this device independent,
|
o_ddr_dqs, o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
|
// we export only the wishbone interface to the RAM.
|
|
// o_ddr_ck_p, o_ddr_ck_n, o_ddr_reset_n, o_ddr_cke,
|
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
|
// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm,
|
|
// io_ddr_dqs_p, io_ddr_dqs_n, io_ddr_data,
|
|
o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata,
|
|
i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err,
|
|
i_ram_dbg,
|
// The SD Card
|
// The SD Card
|
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
|
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
|
// Ethernet control (MDIO) lines
|
// Ethernet control (MDIO) lines
|
o_mdclk, o_mdio, o_mdwe, i_mdio,
|
o_mdclk, o_mdio, o_mdwe, i_mdio,
|
// OLED Control interface (roughly SPI)
|
// OLED Control interface (roughly SPI)
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
// The GPS PMod
|
// The GPS PMod
|
i_gps_pps, i_gps_3df
|
i_gps_pps, i_gps_3df
|
);
|
);
|
parameter ZA=24, ZIPINTS=13;
|
parameter ZA=24, ZIPINTS=14;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
// The bus commander, via an external uart port
|
// The bus commander, via an external uart port
|
input i_rx_stb;
|
input i_rx_stb;
|
input [7:0] i_rx_data;
|
input [7:0] i_rx_data;
|
output wire o_tx_stb;
|
output wire o_tx_stb;
|
| Line 114... |
Line 148... |
// Quad-SPI flash control
|
// Quad-SPI flash control
|
output wire o_qspi_cs_n, o_qspi_sck;
|
output wire o_qspi_cs_n, o_qspi_sck;
|
output wire [3:0] o_qspi_dat;
|
output wire [3:0] o_qspi_dat;
|
input [3:0] i_qspi_dat;
|
input [3:0] i_qspi_dat;
|
output wire [1:0] o_qspi_mod;
|
output wire [1:0] o_qspi_mod;
|
|
//
|
// DDR3 RAM controller
|
// DDR3 RAM controller
|
output wire o_ddr_reset_n, o_ddr_cke,
|
//
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
|
// These would be our RAM control lines. However, these are device,
|
output wire [2:0] o_ddr_dqs;
|
// implementation, and architecture dependent, rather than just simply
|
output wire [13:0] o_ddr_addr;
|
// logic dependent. Therefore, this interface as it exists cannot
|
output wire [2:0] o_ddr_ba;
|
// exist here. Instead, we export a device independent wishbone to
|
output wire [31:0] o_ddr_data;
|
// the RAM rather than the RAM wires themselves.
|
input [31:0] i_ddr_data;
|
//
|
|
// output wire o_ddr_ck_p, o_ddr_ck_n,o_ddr_reset_n, o_ddr_cke,
|
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
|
|
// output wire [2:0] o_ddr_ba;
|
|
// output wire [13:0] o_ddr_addr;
|
|
// output wire o_ddr_odt;
|
|
// output wire [1:0] o_ddr_dm;
|
|
// inout wire [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
|
|
// inout wire [15:0] io_ddr_data;
|
|
//
|
|
output wire o_ram_cyc, o_ram_stb, o_ram_we;
|
|
output wire [25:0] o_ram_addr;
|
|
output wire [31:0] o_ram_wdata;
|
|
input i_ram_ack, i_ram_stall;
|
|
input [31:0] i_ram_rdata;
|
|
input i_ram_err;
|
|
input [31:0] i_ram_dbg;
|
// The SD Card
|
// The SD Card
|
output wire o_sd_sck;
|
output wire o_sd_sck;
|
output wire o_sd_cmd;
|
output wire o_sd_cmd;
|
output wire [3:0] o_sd_data;
|
output wire [3:0] o_sd_data;
|
input i_sd_cmd;
|
input i_sd_cmd;
|
| Line 145... |
Line 196... |
//
|
//
|
//
|
//
|
// Master wishbone wires
|
// Master wishbone wires
|
//
|
//
|
//
|
//
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_err;
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_err, ram_err;
|
wire [31:0] wb_data, wb_addr;
|
wire [31:0] wb_data, wb_addr;
|
reg wb_ack;
|
reg wb_ack;
|
reg [31:0] wb_idata;
|
reg [31:0] wb_idata;
|
|
|
// Interrupts
|
// Interrupts
|
| Line 373... |
Line 424... |
rtc_ack, sdcard_ack,
|
rtc_ack, sdcard_ack,
|
netp_ack, gps_ack, mio_ack, cfg_ack, netb_ack,
|
netp_ack, gps_ack, mio_ack, cfg_ack, netb_ack,
|
mem_ack, flash_ack, ram_ack;
|
mem_ack, flash_ack, ram_ack;
|
reg many_ack, slow_many_ack;
|
reg many_ack, slow_many_ack;
|
reg slow_ack, scop_ack;
|
reg slow_ack, scop_ack;
|
wire [4:0] ack_list;
|
wire [5:0] ack_list;
|
assign ack_list = { ram_ack, flash_ack, mem_ack, netb_ack, cfg_ack };
|
assign ack_list = { ram_ack, flash_ack, mem_ack, netb_ack, netp_ack, slow_ack };
|
initial many_ack = 1'b0;
|
initial many_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
many_ack <= ((ack_list != 5'h10)
|
many_ack <= ((ack_list != 6'h20)
|
&&(ack_list != 5'h8)
|
&&(ack_list != 6'h10)
|
&&(ack_list != 5'h4)
|
&&(ack_list != 6'h8)
|
&&(ack_list != 5'h2)
|
&&(ack_list != 6'h4)
|
&&(ack_list != 5'h1)
|
&&(ack_list != 6'h2)
|
&&(ack_list != 5'h0));
|
&&(ack_list != 6'h1)
|
|
&&(ack_list != 6'h0));
|
/*
|
/*
|
assign many_ack = ( { 2'h0, ram_ack}
|
assign many_ack = ( { 2'h0, ram_ack}
|
+{2'h0, flash_ack }
|
+{2'h0, flash_ack }
|
+{2'h0, mem_ack }
|
+{2'h0, mem_ack }
|
+{2'h0, netb_ack }
|
+{2'h0, netb_ack }
|
+{2'h0, slow_ack } > 3'h1 );
|
+{2'h0, slow_ack } > 3'h1 );
|
*/
|
*/
|
|
|
wire [7:0] slow_ack_list;
|
wire [7:0] slow_ack_list;
|
assign slow_ack_list = { mio_ack, gps_ack, netp_ack,
|
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack,
|
sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };
|
sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };
|
initial slow_many_ack = 1'b0;
|
initial slow_many_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
slow_many_ack <= ((slow_ack_list != 8'h80)
|
slow_many_ack <= ((slow_ack_list != 8'h80)
|
&&(slow_ack_list != 8'h40)
|
&&(slow_ack_list != 8'h40)
|
| Line 407... |
Line 459... |
&&(slow_ack_list != 8'h02)
|
&&(slow_ack_list != 8'h02)
|
&&(slow_ack_list != 8'h01)
|
&&(slow_ack_list != 8'h01)
|
&&(slow_ack_list != 8'h00));
|
&&(slow_ack_list != 8'h00));
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
wb_ack <= (wb_cyc)&&(|{ ram_ack, flash_ack, mem_ack,
|
wb_ack <= (wb_cyc)&&(|ack_list);
|
netb_ack, cfg_ack, slow_ack });
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
slow_ack <= (wb_cyc)&&(|{oled_ack, mio_ack, gps_ack,
|
slow_ack <= (wb_cyc)&&(|slow_ack_list);
|
netp_ack, sdcard_ack, rtc_ack, scop_ack,
|
|
oled_ack, io_ack});
|
|
|
|
//
|
//
|
// Peripheral data lines
|
// Peripheral data lines
|
//
|
//
|
wire [31:0] io_data, oled_data,
|
wire [31:0] io_data, oled_data,
|
| Line 430... |
Line 479... |
if ((ram_ack)||(flash_ack))
|
if ((ram_ack)||(flash_ack))
|
wb_idata <= (ram_ack)?ram_data:flash_data;
|
wb_idata <= (ram_ack)?ram_data:flash_data;
|
else if ((mem_ack)||(netb_ack))
|
else if ((mem_ack)||(netb_ack))
|
wb_idata <= (mem_ack)?mem_data:netb_data;
|
wb_idata <= (mem_ack)?mem_data:netb_data;
|
else
|
else
|
wb_idata <= slow_data;
|
wb_idata <= (netp_ack)?netp_data: slow_data;
|
|
|
// 7 control lines, 8x32 data lines
|
// 7 control lines, 8x32 data lines
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((cfg_ack)||(mio_ack))
|
if ((cfg_ack)||(mio_ack))
|
slow_data <= (cfg_ack) ? cfg_data : mio_data;
|
slow_data <= (cfg_ack) ? cfg_data : mio_data;
|
else if ((gps_ack)||(netp_ack))
|
|
slow_data <= (gps_ack) ? gps_data : netp_data;
|
|
else if ((sdcard_ack)||(rtc_ack))
|
else if ((sdcard_ack)||(rtc_ack))
|
slow_data <= (sdcard_ack)?sdcard_data : rtc_data;
|
slow_data <= (sdcard_ack)?sdcard_data : rtc_data;
|
else if ((scop_ack)|(oled_ack))
|
else if ((scop_ack)|(oled_ack))
|
slow_data <= (scop_ack)?scop_data:oled_data;
|
slow_data <= (scop_ack)?scop_data:oled_data;
|
else
|
else
|
slow_data <= io_data;
|
slow_data <= (gps_ack) ? gps_data : io_data;
|
|
|
//
|
//
|
// Peripheral stall lines
|
// Peripheral stall lines
|
//
|
//
|
// As per the wishbone spec, these cannot be clocked or delayed. They
|
// As per the wishbone spec, these cannot be clocked or delayed. They
|
| Line 463... |
Line 510... |
||((scop_sel)&&(scop_stall)) // Never stalls
|
||((scop_sel)&&(scop_stall)) // Never stalls
|
||((rtc_sel)&&(rtc_stall)) // Never stalls
|
||((rtc_sel)&&(rtc_stall)) // Never stalls
|
||((sdcard_sel)&&(sdcard_stall))// Never stalls
|
||((sdcard_sel)&&(sdcard_stall))// Never stalls
|
||((netp_sel)&&(netp_stall))
|
||((netp_sel)&&(netp_stall))
|
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
|
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
|
||((oled_sel)&&(oled_stall))
|
||((oled_sel)&&(oled_stall)) // Never stalls
|
||((mio_sel)&&(mio_stall))
|
||((mio_sel)&&(mio_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((netb_sel)&&(netb_stall)) // Never stalls
|
||((netb_sel)&&(netb_stall)) // Never stalls
|
||((mem_sel)&&(mem_stall)) // Never stalls
|
||((mem_sel)&&(mem_stall)) // Never stalls
|
||((flash_sel|flctl_sel)&&(flash_stall))
|
||((flash_sel|flctl_sel)&&(flash_stall))
|
| Line 543... |
Line 590... |
wire sel_err; // 5 inputs
|
wire sel_err; // 5 inputs
|
assign sel_err = ( (last_stb)&&(~single_sel_a)&&(~single_sel_b))
|
assign sel_err = ( (last_stb)&&(~single_sel_a)&&(~single_sel_b))
|
||((single_sel_a)&&(single_sel_b))
|
||((single_sel_a)&&(single_sel_b))
|
||((single_sel_a)&&(many_sel_a))
|
||((single_sel_a)&&(many_sel_a))
|
||((single_sel_b)&&(many_sel_b));
|
||((single_sel_b)&&(many_sel_b));
|
assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack);
|
assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack||ram_err);
|
|
|
|
|
// Finally, if we ever encounter a bus error, knowing the address of
|
// Finally, if we ever encounter a bus error, knowing the address of
|
// the error will be important to figuring out how to fix it. Hence,
|
// the error will be important to figuring out how to fix it. Hence,
|
// we grab it here. Be aware, however, that this might not truly be
|
// we grab it here. Be aware, however, that this might not truly be
|
| Line 577... |
Line 624... |
scop_int, flash_int, rtc_pps };
|
scop_int, flash_int, rtc_pps };
|
wire [5:0] board_ints;
|
wire [5:0] board_ints;
|
wire [3:0] w_led;
|
wire [3:0] w_led;
|
wire rtc_ppd;
|
wire rtc_ppd;
|
fastio #(
|
fastio #(
|
.AUXUART_SETUP(30'hd50),
|
.AUXUART_SETUP(30'hd705), // 115200 Baud, 8N1, from 81.25M
|
.GPSUART_SETUP(30'hd20833)
|
.GPSUART_SETUP(30'hd8464), // 9600 Baud, 8N1
|
|
.EXTRACLOCK(0)
|
) runio(i_clk, i_sw, i_btn,
|
) runio(i_clk, i_sw, i_btn,
|
w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
|
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
|
wb_data, io_ack, io_stall, io_data,
|
wb_data, io_ack, io_stall, io_data,
|
| Line 630... |
Line 678... |
//
|
//
|
//
|
//
|
wire gps_tracking, ck_pps;
|
wire gps_tracking, ck_pps;
|
wire [63:0] gps_step;
|
wire [63:0] gps_step;
|
`ifdef RTC_ACCESS
|
`ifdef RTC_ACCESS
|
rtcgps #(32'h15798f) // 2^48 / 200MHz
|
rtcgps
|
|
// #(32'h15798f) // 2^48 / 200MHz
|
|
// #(32'h1a6e3a) // 2^48 / 162.5 MHz
|
|
#(32'h34dc74) // 2^48 / 81.25MHz
|
|
// #(32'h35afe6) // 2^48 / 80.0 MHz
|
thertc(i_clk,
|
thertc(i_clk,
|
wb_cyc, (wb_stb)&&(rtc_sel), wb_we,
|
wb_cyc, (wb_stb)&&(rtc_sel), wb_we,
|
wb_addr[1:0], wb_data,
|
wb_addr[1:0], wb_data,
|
rtc_data, rtc_int, rtc_ppd,
|
rtc_data, rtc_int, rtc_ppd,
|
gps_tracking, ck_pps, gps_step[47:16], rtc_pps);
|
gps_tracking, ck_pps, gps_step[47:16], rtc_pps);
|
| Line 741... |
Line 793... |
wire gps_led;
|
wire gps_led;
|
|
|
//
|
//
|
// GPS CLOCK CONTROL
|
// GPS CLOCK CONTROL
|
//
|
//
|
gpsclock ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
|
gpsclock #(
|
|
.DEFAULT_STEP(32'h834d_c736)
|
|
) ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
|
(wb_stb)&&(gps_sel)&&(~wb_addr[3]),
|
(wb_stb)&&(gps_sel)&&(~wb_addr[3]),
|
wb_we, wb_addr[1:0],
|
wb_we, wb_addr[1:0],
|
wb_data, gck_ack, gck_stall, gck_data,
|
wb_data, gck_ack, gck_stall, gck_data,
|
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
|
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
|
gps_dbg_tick);
|
gps_dbg_tick);
|
| Line 793... |
Line 847... |
assign mio_stall = 1'b0;
|
assign mio_stall = 1'b0;
|
assign netp_stall= 1'b0;
|
assign netp_stall= 1'b0;
|
assign enet_rx_int = 1'b0;
|
assign enet_rx_int = 1'b0;
|
assign enet_tx_int = 1'b0;
|
assign enet_tx_int = 1'b0;
|
|
|
enetctrl #(3)
|
enetctrl #(2)
|
mdio(i_clk, i_rst, wb_cyc, (wb_stb)&&(netb_sel), wb_we,
|
mdio(i_clk, i_rst, wb_cyc, (wb_stb)&&(netb_sel), wb_we,
|
wb_addr[4:0], wb_data[15:0],
|
wb_addr[4:0], wb_data[15:0],
|
netb_ack, netb_stall, netb_data,
|
netb_ack, netb_stall, netb_data,
|
o_mdclk, o_mdio, i_mdio, o_mdwe);
|
o_mdclk, o_mdio, i_mdio, o_mdwe);
|
`else
|
`else
|
| Line 834... |
Line 888... |
|
|
//
|
//
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
//
|
//
|
`ifdef ICAPE_ACCESS
|
`ifdef ICAPE_ACCESS
|
wbicapetwo fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
wire [31:0] cfg_debug;
|
|
wbicapetwo #(.LGDIV(1)) // Divide the clock by two
|
|
fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
wb_addr[4:0], wb_data,
|
wb_addr[4:0], wb_data,
|
cfg_ack, cfg_stall, cfg_data);
|
cfg_ack, cfg_stall, cfg_data, cfg_debug);
|
`else
|
`else
|
reg r_cfg_ack;
|
reg r_cfg_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_cfg_ack <= (cfg_sel)&&(wb_stb);
|
r_cfg_ack <= (cfg_sel)&&(wb_stb);
|
assign cfg_ack = r_cfg_ack;
|
assign cfg_ack = r_cfg_ack;
|
| Line 851... |
Line 907... |
//
|
//
|
// RAM MEMORY ACCESS
|
// RAM MEMORY ACCESS
|
//
|
//
|
// There is no option to turn this off--this RAM must always be
|
// There is no option to turn this off--this RAM must always be
|
// present in the design.
|
// present in the design.
|
memdev #(15) // 32kW, or 128kB, 15 address lines
|
memdev #(.AW(15),
|
|
.EXTRACLOCK(0)) // 32kW, or 128kB, 15 address lines
|
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0],
|
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0],
|
wb_data, mem_ack, mem_stall, mem_data);
|
wb_data, mem_ack, mem_stall, mem_data);
|
|
|
//
|
//
|
// FLASH MEMORY ACCESS
|
// FLASH MEMORY ACCESS
|
| Line 895... |
Line 952... |
//
|
//
|
// DDR3-SDRAM
|
// DDR3-SDRAM
|
//
|
//
|
//
|
//
|
`ifdef SDRAM_ACCESS
|
`ifdef SDRAM_ACCESS
|
wbddrsdram rami(i_clk,
|
//wbddrsdram rami(i_clk,
|
wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
|
// wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
|
ram_ack, ram_stall, ram_data,
|
// ram_ack, ram_stall, ram_data,
|
o_ddr_reset_n, o_ddr_cke,
|
// o_ddr_reset_n, o_ddr_cke,
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
o_ddr_dqs,
|
// o_ddr_dqs,
|
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
|
// o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
|
|
|
|
assign o_ram_cyc = wb_cyc;
|
|
assign o_ram_stb = (wb_stb)&&(ram_sel);
|
|
assign o_ram_we = wb_we;
|
|
assign o_ram_addr = wb_addr[25:0];
|
|
assign o_ram_wdata = wb_data;
|
|
assign ram_ack = i_ram_ack;
|
|
assign ram_stall = i_ram_stall;
|
|
assign ram_data = i_ram_rdata;
|
|
assign ram_err = i_ram_err;
|
|
/*
|
|
migsdram rami(i_clk, i_memref_clk_200mhz, i_rst,
|
|
wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
|
|
4'hf,
|
|
ram_ack, ram_stall, ram_data, ram_err,
|
|
//
|
|
o_ddr_ck_p, o_ddr_ck_n,
|
|
o_ddr_reset_n, o_ddr_cke,
|
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
|
o_ddr_ba, o_ddr_addr,
|
|
o_ddr_odt, o_ddr_dm,
|
|
io_ddr_dqs_p, io_ddr_dqs_n,
|
|
io_ddr_data,
|
|
ram_ready
|
|
);
|
|
*/
|
`else
|
`else
|
assign ram_data = 32'h00;
|
assign ram_data = 32'h00;
|
assign ram_stall = 1'b0;
|
assign ram_stall = 1'b0;
|
reg r_ram_ack;
|
reg r_ram_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 945... |
Line 1028... |
// assign scop_cpu_trigger = zip_scope_data[30];
|
// assign scop_cpu_trigger = zip_scope_data[30];
|
assign scop_cpu_trigger = (wb_stb)&&(mem_sel)&&(~wb_we)
|
assign scop_cpu_trigger = (wb_stb)&&(mem_sel)&&(~wb_we)
|
&&(wb_err)||(zip_scope_data[31]);
|
&&(wb_err)||(zip_scope_data[31]);
|
wbscope #(5'd13) cpuscope(i_clk, 1'b1,(scop_cpu_trigger), zip_scope_data,
|
wbscope #(5'd13) cpuscope(i_clk, 1'b1,(scop_cpu_trigger), zip_scope_data,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_interrupt);
|
scop_cpu_interrupt);
|
|
|
assign scop_a_data = scop_cpu_data;
|
assign scop_a_data = scop_cpu_data;
|
assign scop_a_ack = scop_cpu_ack;
|
assign scop_a_ack = scop_cpu_ack;
|
| Line 964... |
Line 1047... |
// assign scop_cpu_trigger = zip_scope_data[30];
|
// assign scop_cpu_trigger = zip_scope_data[30];
|
assign scop_flash_trigger = (wb_stb)&&((flash_sel)||(flctl_sel));
|
assign scop_flash_trigger = (wb_stb)&&((flash_sel)||(flctl_sel));
|
wbscope #(5'd13) flashscope(i_clk, 1'b1,
|
wbscope #(5'd13) flashscope(i_clk, 1'b1,
|
(scop_flash_trigger), flash_debug,
|
(scop_flash_trigger), flash_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_interrupt);
|
scop_flash_interrupt);
|
|
|
assign scop_a_data = scop_flash_data;
|
assign scop_a_data = scop_flash_data;
|
assign scop_a_ack = scop_flash_ack;
|
assign scop_a_ack = scop_flash_ack;
|
| Line 1005... |
Line 1088... |
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_gps_ack, scop_gps_stall, scop_gps_data,
|
scop_gps_ack, scop_gps_stall, scop_gps_data,
|
scop_gps_interrupt);
|
scop_gps_interrupt);
|
|
|
|
assign scop_b_ack = scop_gps_ack;
|
|
assign scop_b_stall = scop_gps_stall;
|
|
assign scop_b_data = scop_gps_data;
|
|
assign scop_b_interrupt = scop_gps_interrupt;
|
|
`else
|
|
`ifdef CFG_SCOPE
|
|
wire [31:0] scop_cfg_data;
|
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
|
wire [31:0] cfg_debug_2;
|
|
assign cfg_debug_2 = {
|
|
wb_ack, cfg_debug[30:17], slow_ack,
|
|
slow_data[7:0], wb_data[7:0]
|
|
};
|
|
wbscope #(5'd8,32,1) cfgscope(i_clk, 1'b1, (cfg_sel)&&(wb_stb),
|
|
cfg_debug_2,
|
|
// Wishbone interface
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
|
wb_we, wb_addr[0], wb_data,
|
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
|
scop_cfg_interrupt);
|
|
|
|
assign scop_b_data = scop_cfg_data;
|
|
assign scop_b_stall = scop_cfg_stall;
|
|
assign scop_b_ack = scop_cfg_ack;
|
|
assign scop_b_interrupt = scop_cfg_interrupt;
|
`else
|
`else
|
assign scop_b_data = 32'h00;
|
assign scop_b_data = 32'h00;
|
assign scop_b_stall = 1'b0;
|
assign scop_b_stall = 1'b0;
|
assign scop_b_interrupt = 1'b0;
|
assign scop_b_interrupt = 1'b0;
|
|
|
reg r_scop_b_ack;
|
reg r_scop_b_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_scop_b_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b01);
|
r_scop_b_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b01);
|
assign scop_b_ack = r_scop_b_ack;
|
assign scop_b_ack = r_scop_b_ack;
|
`endif
|
`endif
|
|
`endif
|
|
|
//
|
//
|
// SCOPE C
|
// SCOPE C
|
//
|
//
|
wire [31:0] scop_c_data;
|
wire [31:0] scop_c_data;
|
wire scop_c_ack, scop_c_stall, scop_c_interrupt;
|
wire scop_c_ack, scop_c_stall, scop_c_interrupt;
|
//
|
//
|
//`else
|
`ifdef SDRAM_SCOPE
|
|
wire [31:0] scop_sdram_data;
|
|
wire scop_sdram_ack, scop_sdram_stall, scop_sdram_interrupt;
|
|
wire sdram_trigger;
|
|
wire [31:0] sdram_debug;
|
|
assign sdram_trigger = (ram_sel)&&(wb_stb);
|
|
assign sdram_debug= i_ram_dbg;
|
|
|
|
wbscope #(5'd10,32,1) ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
|
|
// Wishbone interface
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
|
|
wb_we, wb_addr[0], wb_data,
|
|
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
|
|
scop_sdram_interrupt);
|
|
|
|
assign scop_c_ack = scop_sdram_ack;
|
|
assign scop_c_stall = scop_sdram_stall;
|
|
assign scop_c_data = scop_sdram_data;
|
|
assign scop_c_interrupt = scop_sdram_interrupt;
|
|
`else
|
assign scop_c_data = 32'h00;
|
assign scop_c_data = 32'h00;
|
assign scop_c_stall = 1'b0;
|
assign scop_c_stall = 1'b0;
|
assign scop_c_interrupt = 1'b0;
|
assign scop_c_interrupt = 1'b0;
|
|
|
reg r_scop_c_ack;
|
reg r_scop_c_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_scop_c_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b10);
|
r_scop_c_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b10);
|
assign scop_c_ack = r_scop_c_ack;
|
assign scop_c_ack = r_scop_c_ack;
|
//`endif
|
`endif
|
|
|
//
|
//
|
// SCOPE D
|
// SCOPE D
|
//
|
//
|
wire [31:0] scop_d_data;
|
wire [31:0] scop_d_data;
|
| Line 1050... |
Line 1179... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_scop_d_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b11);
|
r_scop_d_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b11);
|
assign scop_d_ack = r_scop_d_ack;
|
assign scop_d_ack = r_scop_d_ack;
|
//`endif
|
//`endif
|
|
|
assign scop_int = scop_a_interrupt
|
reg all_scope_interrupts;
|
|| scop_b_interrupt
|
always @(posedge i_clk)
|
|| scop_c_interrupt
|
all_scope_interrupts <= (scop_a_interrupt)
|
|| scop_d_interrupt;
|
|| (scop_b_interrupt)
|
|
|| (scop_c_interrupt)
|
|
|| (scop_d_interrupt);
|
|
assign scop_int = all_scope_interrupts;
|
|
|
|
// Scopes don't stall, so this line is more formality than anything
|
|
// else.
|
assign scop_stall = ((wb_addr[2:1]==2'b0)?scop_a_stall
|
assign scop_stall = ((wb_addr[2:1]==2'b0)?scop_a_stall
|
: ((wb_addr[2:1]==2'b01)?scop_b_stall
|
: ((wb_addr[2:1]==2'b01)?scop_b_stall
|
: ((wb_addr[2:1]==2'b11)?scop_c_stall
|
: ((wb_addr[2:1]==2'b10)?scop_c_stall
|
: scop_d_stall))); // Will always be 1'b0;
|
: scop_d_stall))); // Will always be 1'b0;
|
initial scop_ack = 1'b0;
|
initial scop_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
scop_ack <= scop_a_ack | scop_b_ack | scop_c_ack | scop_d_ack;
|
scop_ack <= scop_a_ack | scop_b_ack | scop_c_ack | scop_d_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
