| Line 262... |
Line 262... |
// Fast interrupts
|
// Fast interrupts
|
sdcard_int, auxtx_int, auxrx_int, enet_tx_int, enet_rx_int,
|
sdcard_int, auxtx_int, auxrx_int, enet_tx_int, enet_rx_int,
|
gpsrx_int, rtc_pps
|
gpsrx_int, rtc_pps
|
};
|
};
|
|
|
zipsystem #( .RESET_ADDRESS(24'h08000),
|
zipsystem #( .RESET_ADDRESS(24'h0480000),
|
.ADDRESS_WIDTH(ZA),
|
.ADDRESS_WIDTH(ZA),
|
.LGICACHE(10),
|
.LGICACHE(10),
|
.START_HALTED(1),
|
.START_HALTED(1),
|
.EXTERNAL_INTERRUPTS(ZIPINTS),
|
.EXTERNAL_INTERRUPTS(ZIPINTS),
|
.HIGHSPEED_CPU(0))
|
.HIGHSPEED_CPU(0))
|
| Line 392... |
Line 392... |
assign ram_sel = (skipaddr[4]);
|
assign ram_sel = (skipaddr[4]);
|
assign flash_sel = (skipaddr[4:3]==2'b01);
|
assign flash_sel = (skipaddr[4:3]==2'b01);
|
assign mem_sel = (skipaddr[4:2]==3'b001);
|
assign mem_sel = (skipaddr[4:2]==3'b001);
|
assign netb_sel = (skipaddr[4:1]==4'b0001);
|
assign netb_sel = (skipaddr[4:1]==4'b0001);
|
assign io_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b000);
|
assign io_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b000);
|
assign scop_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b00100);
|
assign scop_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0010_0);
|
assign rtc_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b001010);
|
assign rtc_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0010_10);
|
assign sdcard_sel= (~|skipaddr)&&(wb_addr[7:2]==6'b001011);
|
assign sdcard_sel= (~|skipaddr)&&(wb_addr[7:2]==6'b0010_11);
|
assign netp_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b001101);
|
//assign gps_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_00);
|
assign oled_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b001110);
|
assign oled_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_01);
|
assign gps_sel = (~|skipaddr)&&( (wb_addr[7:2]==6'b001100)
|
assign netp_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0011_1);
|
|| (wb_addr[7:3]==5'b01000));
|
assign gps_sel = (~|skipaddr)&&( (wb_addr[7:2]==6'b0011_00)
|
|
|| (wb_addr[7:3]==5'b0100_0));
|
assign mio_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b101);
|
assign mio_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b101);
|
assign flctl_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b110);
|
assign flctl_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b110);
|
assign cfg_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b111);
|
assign cfg_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b111);
|
|
|
wire skiperr;
|
wire skiperr;
|
| Line 737... |
Line 738... |
//
|
//
|
// OLEDrgb device control
|
// OLEDrgb device control
|
//
|
//
|
//
|
//
|
`ifdef OLEDRGB_ACCESS
|
`ifdef OLEDRGB_ACCESS
|
wboled rgbctrl(i_clk,
|
wboled
|
|
.#( .CBITS(4))// Div ck by 2^4=16, words take 200ns@81.25MHz
|
|
rgbctrl(i_clk,
|
wb_cyc, (wb_stb)&&(oled_sel), wb_we,
|
wb_cyc, (wb_stb)&&(oled_sel), wb_we,
|
wb_addr[1:0], wb_data,
|
wb_addr[1:0], wb_data,
|
oled_ack, oled_stall, oled_data,
|
oled_ack, oled_stall, oled_data,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
{ o_oled_reset_n, o_oled_vccen, o_oled_pmoden },
|
{ o_oled_reset_n, o_oled_vccen, o_oled_pmoden },
|
