| Line 72... |
Line 72... |
//
|
//
|
//
|
//
|
// SCOPE POSITION ZERO
|
// SCOPE POSITION ZERO
|
//
|
//
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_ACCESS
|
`define FLASH_SCOPE // Position zero
|
// `define FLASH_SCOPE // Position zero
|
`else
|
`endif
|
`ifdef ZIPCPU
|
`ifdef ZIPCPU
|
// `define CPU_SCOPE // Position zero
|
`ifndef FLASH_SCOPE
|
|
`define CPU_SCOPE // Position zero
|
`endif
|
`endif
|
`endif
|
`endif
|
//
|
//
|
// SCOPE POSITION ONE
|
// SCOPE POSITION ONE
|
//
|
//
|
// `define GPS_SCOPE // Position one
|
// `define GPS_SCOPE // Position one
|
`ifdef ICAPE_ACCESS
|
// `ifdef ICAPE_ACCESS
|
`define CFG_SCOPE // Position one
|
// `define CFG_SCOPE // Position one
|
`endif
|
// `endif
|
|
// `define WBU_SCOPE
|
//
|
//
|
// SCOPE POSITION TWO
|
// SCOPE POSITION TWO
|
//
|
//
|
`ifdef SDRAM_ACCESS
|
`ifdef SDRAM_ACCESS
|
`define SDRAM_SCOPE // Position two
|
// `define SDRAM_SCOPE // Position two
|
|
`endif
|
|
//
|
|
// SCOPE POSITION THREE
|
|
//
|
|
`ifdef ETHERNET_ACCESS
|
|
`define ENET_SCOPE
|
`endif
|
`endif
|
// `define ENET_SCOPE
|
|
//
|
//
|
//
|
//
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
// CNC
|
// CNC
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
| Line 117... |
Line 124... |
o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata,
|
o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata,
|
i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err,
|
i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err,
|
i_ram_dbg,
|
i_ram_dbg,
|
// The SD Card
|
// The SD Card
|
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
|
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
|
|
// Ethernet control (packets) lines
|
|
o_net_reset_n, i_net_rx_clk, i_net_col, i_net_crs, i_net_dv,
|
|
i_net_rxd, i_net_rxerr,
|
|
i_net_tx_clk, o_net_tx_en, o_net_txd,
|
// Ethernet control (MDIO) lines
|
// Ethernet control (MDIO) lines
|
o_mdclk, o_mdio, o_mdwe, i_mdio,
|
o_mdclk, o_mdio, o_mdwe, i_mdio,
|
// OLED Control interface (roughly SPI)
|
// OLED Control interface (roughly SPI)
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
// The GPS PMod
|
// The GPS PMod
|
i_gps_pps, i_gps_3df
|
i_gps_pps, i_gps_3df
|
);
|
);
|
parameter ZA=24, ZIPINTS=14;
|
parameter ZA=28, ZIPINTS=14, RESET_ADDRESS=28'h04e0000;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
// The bus commander, via an external uart port
|
// The bus commander, via an external uart port
|
input i_rx_stb;
|
input i_rx_stb;
|
input [7:0] i_rx_data;
|
input [7:0] i_rx_data;
|
output wire o_tx_stb;
|
output wire o_tx_stb;
|
| Line 180... |
Line 191... |
output wire o_sd_cmd;
|
output wire o_sd_cmd;
|
output wire [3:0] o_sd_data;
|
output wire [3:0] o_sd_data;
|
input i_sd_cmd;
|
input i_sd_cmd;
|
input [3:0] i_sd_data;
|
input [3:0] i_sd_data;
|
input i_sd_detect;
|
input i_sd_detect;
|
|
// Ethernet control
|
|
output wire o_net_reset_n;
|
|
input i_net_rx_clk, i_net_col, i_net_crs, i_net_dv;
|
|
input [3:0] i_net_rxd;
|
|
input i_net_rxerr;
|
|
input i_net_tx_clk;
|
|
output wire o_net_tx_en;
|
|
output wire [3:0] o_net_txd;
|
// Ethernet control (MDIO)
|
// Ethernet control (MDIO)
|
output wire o_mdclk, o_mdio, o_mdwe;
|
output wire o_mdclk, o_mdio, o_mdwe;
|
input i_mdio;
|
input i_mdio;
|
// OLEDRGB interface
|
// OLEDRGB interface
|
output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
|
output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
|
| Line 224... |
Line 243... |
// And then headed back home
|
// And then headed back home
|
wire w_interrupt;
|
wire w_interrupt;
|
// Oh, and the debug control for the ZIP CPU
|
// Oh, and the debug control for the ZIP CPU
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
wire [31:0] zip_dbg_data;
|
wire [31:0] zip_dbg_data;
|
|
`ifdef WBU_SCOPE
|
|
wire [31:0] wbu_debug;
|
|
`endif
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
(wbu_zip_sel)?zip_dbg_ack:wbu_ack,
|
(wbu_zip_sel)?zip_dbg_ack:wbu_ack,
|
(wbu_zip_sel)?zip_dbg_stall:wbu_stall,
|
(wbu_zip_sel)?zip_dbg_stall:wbu_stall,
|
wbu_err,
|
wbu_err,
|
(wbu_zip_sel)?zip_dbg_data:wbu_idata,
|
(wbu_zip_sel)?zip_dbg_data:wbu_idata,
|
w_interrupt,
|
w_interrupt,
|
o_tx_stb, o_tx_data, i_tx_busy);
|
o_tx_stb, o_tx_data, i_tx_busy
|
|
// , wbu_debug
|
|
);
|
|
|
|
`ifdef WBU_SCOPE
|
// assign o_dbg = (wbu_ack)&&(wbu_cyc);
|
// assign o_dbg = (wbu_ack)&&(wbu_cyc);
|
|
assign wbu_debug = { wbu_cyc, wbu_stb, wbu_we, wbu_ack, wbu_stall,
|
|
wbu_err, wbu_zip_sel,
|
|
wbu_addr[8:0],
|
|
wbu_data[7:0],
|
|
wbu_idata[7:0] };
|
|
`endif
|
|
|
wire zip_cpu_int; // True if the CPU suddenly halts
|
wire zip_cpu_int; // True if the CPU suddenly halts
|
`ifdef ZIPCPU
|
`ifdef ZIPCPU
|
// Are we trying to access the ZipCPU? Such accesses must be special,
|
// Are we trying to access the ZipCPU? Such accesses must be special,
|
// because they must succeed regardless of whether or not the ZipCPU
|
// because they must succeed regardless of whether or not the ZipCPU
|
| Line 262... |
Line 293... |
// Fast interrupts
|
// Fast interrupts
|
sdcard_int, auxtx_int, auxrx_int, enet_tx_int, enet_rx_int,
|
sdcard_int, auxtx_int, auxrx_int, enet_tx_int, enet_rx_int,
|
gpsrx_int, rtc_pps
|
gpsrx_int, rtc_pps
|
};
|
};
|
|
|
zipsystem #( .RESET_ADDRESS(24'h0480000),
|
zipsystem #( .RESET_ADDRESS(RESET_ADDRESS),
|
.ADDRESS_WIDTH(ZA),
|
.ADDRESS_WIDTH(ZA),
|
.LGICACHE(10),
|
.LGICACHE(10),
|
.START_HALTED(1),
|
.START_HALTED(1),
|
.EXTERNAL_INTERRUPTS(ZIPINTS),
|
.EXTERNAL_INTERRUPTS(ZIPINTS),
|
.HIGHSPEED_CPU(0))
|
.HIGHSPEED_CPU(0))
|
| Line 278... |
Line 309... |
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
wbu_data,
|
wbu_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
`ifdef CPU_DEBUG
|
`ifdef CPU_SCOPE
|
, zip_scope_data
|
, zip_scope_data
|
`endif
|
`endif
|
);
|
);
|
`else // ZIP_SYSTEM
|
`else // ZIP_SYSTEM
|
wire w_zip_cpu_int_ignored;
|
wire w_zip_cpu_int_ignored;
|
zipbones #( .RESET_ADDRESS(24'h08000),
|
zipbones #( .RESET_ADDRESS(RESET_ADDRESS),
|
.ADDRESS_WIDTH(ZA),
|
.ADDRESS_WIDTH(ZA),
|
.LGICACHE(10),
|
.LGICACHE(10),
|
.START_HALTED(1),
|
.START_HALTED(1),
|
.HIGHSPEED_CPU(0))
|
.HIGHSPEED_CPU(0))
|
zippy(i_clk, i_rst,
|
zippy(i_clk, i_rst,
|
| Line 299... |
Line 330... |
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
wbu_data,
|
wbu_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
`ifdef CPU_DEBUG
|
`ifdef CPU_SCOPE
|
, zip_scope_data
|
, zip_scope_data
|
`endif
|
`endif
|
);
|
);
|
assign zip_cpu_int = 1'b0;
|
assign zip_cpu_int = 1'b0;
|
`endif // ZIP_SYSTEM v ZIP_BONES
|
`endif // ZIP_SYSTEM v ZIP_BONES
|
| Line 326... |
Line 357... |
wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
|
wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
|
// The ZIP CPU Master -- Gets the priority slot
|
// The ZIP CPU Master -- Gets the priority slot
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
|
zip_ack, zip_stall, zip_err,
|
zip_ack, zip_stall, zip_err,
|
// The UART interface Master
|
// The UART interface Master
|
(wbu_cyc)&&(~wbu_zip_sel), (wbu_stb)&&(~wbu_zip_sel), wbu_we,
|
(wbu_cyc)&&(!wbu_zip_sel), (wbu_stb)&&(!wbu_zip_sel), wbu_we,
|
wbu_addr, wbu_data,
|
wbu_addr, wbu_data,
|
wbu_ack, wbu_stall, wbu_err,
|
wbu_ack, wbu_stall, wbu_err,
|
// Common bus returns
|
// Common bus returns
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_ack, dwb_stall, dwb_err);
|
dwb_ack, dwb_stall, dwb_err);
|
| Line 421... |
Line 452... |
// ACK for both flctl_sel (the control line select), as well as the
|
// ACK for both flctl_sel (the control line select), as well as the
|
// flash_sel (the memory line select). Hence we have one fewer ack
|
// flash_sel (the memory line select). Hence we have one fewer ack
|
// line.
|
// line.
|
wire io_ack, oled_ack,
|
wire io_ack, oled_ack,
|
rtc_ack, sdcard_ack,
|
rtc_ack, sdcard_ack,
|
netp_ack, gps_ack, mio_ack, cfg_ack, netb_ack,
|
net_ack, gps_ack, mio_ack, cfg_ack,
|
mem_ack, flash_ack, ram_ack;
|
mem_ack, flash_ack, ram_ack;
|
reg many_ack, slow_many_ack;
|
reg many_ack, slow_many_ack;
|
reg slow_ack, scop_ack;
|
reg slow_ack, scop_ack;
|
wire [5:0] ack_list;
|
wire [4:0] ack_list;
|
assign ack_list = { ram_ack, flash_ack, mem_ack, netb_ack, netp_ack, slow_ack };
|
assign ack_list = { ram_ack, flash_ack, mem_ack, net_ack, slow_ack };
|
initial many_ack = 1'b0;
|
initial many_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
many_ack <= ((ack_list != 6'h20)
|
many_ack <= ((ack_list != 5'h10)
|
&&(ack_list != 6'h10)
|
&&(ack_list != 5'h8)
|
&&(ack_list != 6'h8)
|
&&(ack_list != 5'h4)
|
&&(ack_list != 6'h4)
|
&&(ack_list != 5'h2)
|
&&(ack_list != 6'h2)
|
&&(ack_list != 5'h1)
|
&&(ack_list != 6'h1)
|
&&(ack_list != 5'h0));
|
&&(ack_list != 6'h0));
|
|
/*
|
/*
|
assign many_ack = ( { 2'h0, ram_ack}
|
assign many_ack = ( { 2'h0, ram_ack}
|
+{2'h0, flash_ack }
|
+{2'h0, flash_ack }
|
+{2'h0, mem_ack }
|
+{2'h0, mem_ack }
|
+{2'h0, netb_ack }
|
|
+{2'h0, slow_ack } > 3'h1 );
|
+{2'h0, slow_ack } > 3'h1 );
|
*/
|
*/
|
|
|
wire [7:0] slow_ack_list;
|
wire [7:0] slow_ack_list;
|
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack,
|
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack,
|
| Line 469... |
Line 498... |
//
|
//
|
// Peripheral data lines
|
// Peripheral data lines
|
//
|
//
|
wire [31:0] io_data, oled_data,
|
wire [31:0] io_data, oled_data,
|
rtc_data, sdcard_data,
|
rtc_data, sdcard_data,
|
netp_data, gps_data, mio_data, cfg_data, netb_data,
|
net_data, gps_data, mio_data, cfg_data,
|
mem_data, flash_data, ram_data;
|
mem_data, flash_data, ram_data;
|
reg [31:0] slow_data, scop_data;
|
reg [31:0] slow_data, scop_data;
|
|
|
// 4 control lines, 5x32 data lines ...
|
// 4 control lines, 5x32 data lines ...
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((ram_ack)||(flash_ack))
|
if ((ram_ack)||(flash_ack))
|
wb_idata <= (ram_ack)?ram_data:flash_data;
|
wb_idata <= (ram_ack)?ram_data:flash_data;
|
else if ((mem_ack)||(netb_ack))
|
else if ((mem_ack)||(net_ack))
|
wb_idata <= (mem_ack)?mem_data:netb_data;
|
wb_idata <= (mem_ack)?mem_data:net_data;
|
else
|
else
|
wb_idata <= (netp_ack)?netp_data: slow_data;
|
wb_idata <= slow_data;
|
|
|
// 7 control lines, 8x32 data lines
|
// 7 control lines, 8x32 data lines
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((cfg_ack)||(mio_ack))
|
if ((cfg_ack)||(mio_ack))
|
slow_data <= (cfg_ack) ? cfg_data : mio_data;
|
slow_data <= (cfg_ack) ? cfg_data : mio_data;
|
| Line 501... |
Line 530... |
// As per the wishbone spec, these cannot be clocked or delayed. They
|
// As per the wishbone spec, these cannot be clocked or delayed. They
|
// *must* be done via combinatorial logic.
|
// *must* be done via combinatorial logic.
|
//
|
//
|
wire io_stall, scop_stall, oled_stall,
|
wire io_stall, scop_stall, oled_stall,
|
rtc_stall, sdcard_stall,
|
rtc_stall, sdcard_stall,
|
netp_stall, gps_stall, mio_stall, cfg_stall, netb_stall,
|
net_stall, gps_stall, mio_stall, cfg_stall, netb_stall,
|
mem_stall, flash_stall, ram_stall,
|
mem_stall, flash_stall, ram_stall,
|
many_stall;
|
many_stall;
|
assign wb_stall = (wb_cyc)&&(
|
assign wb_stall = (wb_cyc)&&(
|
((io_sel)&&(io_stall)) // Never stalls
|
((io_sel)&&(io_stall)) // Never stalls
|
||((scop_sel)&&(scop_stall)) // Never stalls
|
||((scop_sel)&&(scop_stall)) // Never stalls
|
||((rtc_sel)&&(rtc_stall)) // Never stalls
|
||((rtc_sel)&&(rtc_stall)) // Never stalls
|
||((sdcard_sel)&&(sdcard_stall))// Never stalls
|
||((sdcard_sel)&&(sdcard_stall))// Never stalls
|
||((netp_sel)&&(netp_stall))
|
||((netp_sel)&&(net_stall)) // Never stalls
|
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
|
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
|
||((oled_sel)&&(oled_stall)) // Never stalls
|
||((oled_sel)&&(oled_stall)) // Never stalls
|
||((mio_sel)&&(mio_stall))
|
||((mio_sel)&&(mio_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((netb_sel)&&(netb_stall)) // Never stalls
|
||((netb_sel)&&(net_stall)) // Never stalls
|
||((mem_sel)&&(mem_stall)) // Never stalls
|
||((mem_sel)&&(mem_stall)) // Never stalls
|
||((flash_sel|flctl_sel)&&(flash_stall))
|
||((flash_sel|flctl_sel)&&(flash_stall))
|
||((ram_sel)&&(ram_stall)));
|
||((ram_sel)&&(ram_stall)));
|
|
|
|
|
| Line 739... |
Line 768... |
// OLEDrgb device control
|
// OLEDrgb device control
|
//
|
//
|
//
|
//
|
`ifdef OLEDRGB_ACCESS
|
`ifdef OLEDRGB_ACCESS
|
wboled
|
wboled
|
.#( .CBITS(4))// Div ck by 2^4=16, words take 200ns@81.25MHz
|
#( .CBITS(4))// Div ck by 2^4=16, words take 200ns@81.25MHz
|
rgbctrl(i_clk,
|
rgbctrl(i_clk,
|
wb_cyc, (wb_stb)&&(oled_sel), wb_we,
|
wb_cyc, (wb_stb)&&(oled_sel), wb_we,
|
wb_addr[1:0], wb_data,
|
wb_addr[1:0], wb_data,
|
oled_ack, oled_stall, oled_data,
|
oled_ack, oled_stall, oled_data,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
| Line 835... |
Line 864... |
|
|
//
|
//
|
// ETHERNET DEVICE ACCESS
|
// ETHERNET DEVICE ACCESS
|
//
|
//
|
`ifdef ETHERNET_ACCESS
|
`ifdef ETHERNET_ACCESS
|
reg r_mio_ack, r_netb_ack, r_netp_ack;
|
`ifdef ENET_SCOPE
|
always @(posedge i_clk)
|
wire [31:0] txnet_data;
|
r_mio_ack <= (wb_stb)&&(mio_sel);
|
`endif
|
always @(posedge i_clk)
|
|
r_netp_ack <= (wb_stb)&&(netp_sel);
|
|
assign mio_ack = r_mio_ack;
|
|
assign netp_ack = r_netp_ack;
|
|
|
|
assign mio_data = 32'h00;
|
enetpackets #(12)
|
assign netp_data = 32'h00;
|
netctrl(i_clk, i_rst, wb_cyc,(wb_stb)&&((netp_sel)||(netb_sel)),
|
assign mio_stall = 1'b0;
|
wb_we, { (netb_sel), wb_addr[10:0] }, wb_data,
|
assign netp_stall= 1'b0;
|
net_ack, net_stall, net_data,
|
assign enet_rx_int = 1'b0;
|
o_net_reset_n,
|
assign enet_tx_int = 1'b0;
|
i_net_rx_clk, i_net_col, i_net_crs, i_net_dv, i_net_rxd,
|
|
i_net_rxerr,
|
|
i_net_tx_clk, o_net_tx_en, o_net_txd,
|
|
enet_rx_int, enet_tx_int
|
|
`ifdef ENET_SCOPE
|
|
, txnet_data
|
|
`endif
|
|
);
|
|
|
|
wire [31:0] mdio_debug;
|
enetctrl #(2)
|
enetctrl #(2)
|
mdio(i_clk, i_rst, wb_cyc, (wb_stb)&&(netb_sel), wb_we,
|
mdio(i_clk, i_rst, wb_cyc, (wb_stb)&&(mio_sel), wb_we,
|
wb_addr[4:0], wb_data[15:0],
|
wb_addr[4:0], wb_data[15:0],
|
netb_ack, netb_stall, netb_data,
|
mio_ack, mio_stall, mio_data,
|
o_mdclk, o_mdio, i_mdio, o_mdwe);
|
o_mdclk, o_mdio, i_mdio, o_mdwe,
|
|
mdio_debug);
|
`else
|
`else
|
reg r_mio_ack, r_netb_ack, r_netp_ack;
|
reg r_mio_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_mio_ack <= (wb_stb)&&(mio_sel);
|
r_mio_ack <= (wb_stb)&&(mio_sel);
|
always @(posedge i_clk)
|
|
r_netp_ack <= (wb_stb)&&(netp_sel);
|
|
assign mio_ack = r_mio_ack;
|
assign mio_ack = r_mio_ack;
|
assign netp_ack = r_netp_ack;
|
|
|
|
assign mio_data = 32'h00;
|
assign mio_data = 32'h00;
|
assign netp_data = 32'h00;
|
|
assign mio_stall = 1'b0;
|
assign mio_stall = 1'b0;
|
assign netp_stall= 1'b0;
|
|
assign enet_rx_int = 1'b0;
|
assign enet_rx_int = 1'b0;
|
assign enet_tx_int = 1'b0;
|
assign enet_tx_int = 1'b0;
|
|
|
//
|
//
|
// 2kW memory, 1kW for each of transmit and receive. (Max pkt length
|
// 2kW memory, 1kW for each of transmit and receive. (Max pkt length
|
// is 512W, so this allows for two 512W in memory.) Since we don't
|
// is 512W, so this allows for two 512W in memory.) Since we don't
|
// really have ethernet without ETHERNET_ACCESS defined, this just
|
// really have ethernet without ETHERNET_ACCESS defined, this just
|
// consumes resources for us so we have an idea of what might be
|
// consumes resources for us so we have an idea of what might be
|
// available when we do have ETHERNET_ACCESS defined.
|
// available when we do have ETHERNET_ACCESS defined.
|
//
|
//
|
memdev #(11) enet_buffers(i_clk, wb_cyc, (wb_stb)&&(netb_sel), wb_we,
|
memdev #(11) enet_buffers(i_clk, wb_cyc, (wb_stb)&&((netb_sel)||(netp_sel)), wb_we,
|
wb_addr[10:0], wb_data, netb_ack, netb_stall, netb_data);
|
wb_addr[10:0], wb_data, net_ack, net_stall, net_data);
|
assign o_mdclk = 1'b1;
|
assign o_mdclk = 1'b1;
|
assign o_mdio = 1'b1;
|
assign o_mdio = 1'b1;
|
assign o_mdwe = 1'b1;
|
assign o_mdwe = 1'b1;
|
|
|
`endif
|
`endif
|
| Line 919... |
Line 948... |
|
|
//
|
//
|
// FLASH MEMORY ACCESS
|
// FLASH MEMORY ACCESS
|
//
|
//
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_SCOPE
|
// `ifdef FLASH_SCOPE
|
wire [31:0] flash_debug;
|
wire [31:0] flash_debug;
|
`endif
|
// `endif
|
wire w_ignore_cmd_accepted;
|
wire w_ignore_cmd_accepted;
|
eqspiflash flashmem(i_clk, i_rst,
|
eqspiflash flashmem(i_clk, i_rst,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_addr[21:0], wb_data,
|
wb_addr[21:0], wb_data,
|
flash_ack, flash_stall, flash_data,
|
flash_ack, flash_stall, flash_data,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
flash_int, w_ignore_cmd_accepted
|
flash_int, w_ignore_cmd_accepted
|
`ifdef FLASH_SCOPE
|
// `ifdef FLASH_SCOPE
|
, flash_debug
|
, flash_debug
|
`endif
|
// `endif
|
);
|
);
|
`else
|
`else
|
assign o_qspi_sck = 1'b1;
|
assign o_qspi_sck = 1'b1;
|
assign o_qspi_cs_n= 1'b1;
|
assign o_qspi_cs_n= 1'b1;
|
assign o_qspi_mod = 2'b01;
|
assign o_qspi_mod = 2'b01;
|
| Line 1026... |
Line 1055... |
wire scop_a_ack, scop_a_stall, scop_a_interrupt;
|
wire scop_a_ack, scop_a_stall, scop_a_interrupt;
|
`ifdef CPU_SCOPE
|
`ifdef CPU_SCOPE
|
wire [31:0] scop_cpu_data;
|
wire [31:0] scop_cpu_data;
|
wire scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt;
|
wire scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt;
|
wire scop_cpu_trigger;
|
wire scop_cpu_trigger;
|
// assign scop_cpu_trigger = zip_scope_data[30];
|
assign scop_cpu_trigger = (zip_scope_data[31]);
|
assign scop_cpu_trigger = (wb_stb)&&(mem_sel)&&(~wb_we)
|
wbscope #( .LGMEM(5'd13),
|
&&(wb_err)||(zip_scope_data[31]);
|
.DEFAULT_HOLDOFF(32))
|
wbscope #(5'd13) cpuscope(i_clk, 1'b1,(scop_cpu_trigger), zip_scope_data,
|
cpuscope(i_clk, 1'b1,(scop_cpu_trigger),zip_scope_data,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
i_clk, wb_cyc,
|
|
((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_interrupt);
|
scop_cpu_interrupt);
|
|
|
assign scop_a_data = scop_cpu_data;
|
assign scop_a_data = scop_cpu_data;
|
| Line 1045... |
Line 1075... |
`else
|
`else
|
`ifdef FLASH_SCOPE
|
`ifdef FLASH_SCOPE
|
wire [31:0] scop_flash_data;
|
wire [31:0] scop_flash_data;
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
wire scop_flash_trigger;
|
wire scop_flash_trigger;
|
// assign scop_cpu_trigger = zip_scope_data[30];
|
|
assign scop_flash_trigger = (wb_stb)&&((flash_sel)||(flctl_sel));
|
assign scop_flash_trigger = (wb_stb)&&((flash_sel)||(flctl_sel));
|
wbscope #(5'd13) flashscope(i_clk, 1'b1,
|
wbscope #(5'd11) flashscope(i_clk, 1'b1,
|
(scop_flash_trigger), flash_debug,
|
(scop_flash_trigger), flash_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
| Line 1118... |
Line 1147... |
assign scop_b_data = scop_cfg_data;
|
assign scop_b_data = scop_cfg_data;
|
assign scop_b_stall = scop_cfg_stall;
|
assign scop_b_stall = scop_cfg_stall;
|
assign scop_b_ack = scop_cfg_ack;
|
assign scop_b_ack = scop_cfg_ack;
|
assign scop_b_interrupt = scop_cfg_interrupt;
|
assign scop_b_interrupt = scop_cfg_interrupt;
|
`else
|
`else
|
|
`ifdef WBU_SCOPE
|
|
wire [31:0] scop_wbu_data;
|
|
wire scop_wbu_ack, scop_wbu_stall, scop_wbu_interrupt;
|
|
wbscope #(5'd10,32,1) wbuscope(i_clk, 1'b1, (flash_sel)&&(wb_stb),
|
|
wbu_debug,
|
|
// Wishbone interface
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
|
wb_we, wb_addr[0], wb_data,
|
|
scop_wbu_ack, scop_wbu_stall, scop_wbu_data,
|
|
scop_wbu_interrupt);
|
|
|
|
assign scop_b_data = scop_wbu_data;
|
|
assign scop_b_stall = scop_wbu_stall;
|
|
assign scop_b_ack = scop_wbu_ack;
|
|
assign scop_b_interrupt = scop_wbu_interrupt;
|
|
`else
|
assign scop_b_data = 32'h00;
|
assign scop_b_data = 32'h00;
|
assign scop_b_stall = 1'b0;
|
assign scop_b_stall = 1'b0;
|
assign scop_b_interrupt = 1'b0;
|
assign scop_b_interrupt = 1'b0;
|
|
|
reg r_scop_b_ack;
|
reg r_scop_b_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_scop_b_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b01);
|
r_scop_b_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b01);
|
assign scop_b_ack = r_scop_b_ack;
|
assign scop_b_ack = r_scop_b_ack;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
`endif
|
|
|
//
|
//
|
// SCOPE C
|
// SCOPE C
|
//
|
//
|
wire [31:0] scop_c_data;
|
wire [31:0] scop_c_data;
|
| Line 1143... |
Line 1189... |
wire sdram_trigger;
|
wire sdram_trigger;
|
wire [31:0] sdram_debug;
|
wire [31:0] sdram_debug;
|
assign sdram_trigger = (ram_sel)&&(wb_stb);
|
assign sdram_trigger = (ram_sel)&&(wb_stb);
|
assign sdram_debug= i_ram_dbg;
|
assign sdram_debug= i_ram_dbg;
|
|
|
wbscope #(5'd10,32,1) ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
|
wbscope #(5'd9,32,1) ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
|
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
|
scop_sdram_interrupt);
|
scop_sdram_interrupt);
|
| Line 1171... |
Line 1217... |
// SCOPE D
|
// SCOPE D
|
//
|
//
|
wire [31:0] scop_d_data;
|
wire [31:0] scop_d_data;
|
wire scop_d_ack, scop_d_stall, scop_d_interrupt;
|
wire scop_d_ack, scop_d_stall, scop_d_interrupt;
|
//
|
//
|
//`else
|
`ifdef ENET_SCOPE
|
|
wire [31:0] scop_net_data;
|
|
wire scop_net_ack, scop_net_stall, scop_net_interrupt;
|
|
|
|
/*
|
|
wbscope #(5'd8,32,1)
|
|
net_scope(i_clk, 1'b1, !mdio_debug[1], mdio_debug,
|
|
// Wishbone interface
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)),
|
|
wb_we, wb_addr[0], wb_data,
|
|
scop_net_ack, scop_net_stall, scop_net_data,
|
|
scop_net_interrupt);
|
|
*/
|
|
|
|
// 5'd8 is sufficient for small packets, and indeed the minimum for
|
|
// watching any packets--as the minimum packet size is 64 bytes, or
|
|
// 128 nibbles.
|
|
wbscope #(5'd9,32,0)
|
|
net_scope(i_net_rx_clk, 1'b1, txnet_data[31], txnet_data,
|
|
// Wishbone interface
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)),
|
|
wb_we, wb_addr[0], wb_data,
|
|
scop_net_ack, scop_net_stall, scop_net_data,
|
|
scop_net_interrupt);
|
|
|
|
assign scop_d_ack = scop_net_ack;
|
|
assign scop_d_stall = scop_net_stall;
|
|
assign scop_d_data = scop_net_data;
|
|
assign scop_d_interrupt = scop_net_interrupt;
|
|
|
|
`else
|
assign scop_d_data = 32'h00;
|
assign scop_d_data = 32'h00;
|
assign scop_d_stall = 1'b0;
|
assign scop_d_stall = 1'b0;
|
assign scop_d_interrupt = 1'b0;
|
assign scop_d_interrupt = 1'b0;
|
|
|
reg r_scop_d_ack;
|
reg r_scop_d_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_scop_d_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b11);
|
r_scop_d_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b11);
|
assign scop_d_ack = r_scop_d_ack;
|
assign scop_d_ack = r_scop_d_ack;
|
//`endif
|
`endif
|
|
|
reg all_scope_interrupts;
|
reg all_scope_interrupts;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
all_scope_interrupts <= (scop_a_interrupt)
|
all_scope_interrupts <= (scop_a_interrupt)
|
|| (scop_b_interrupt)
|
|| (scop_b_interrupt)
|
